Method of programming a nonvolatile memory cell by reverse biasing a diode steering element to set a storage element

1. A method of programming a nonvolatile memory cell comprising a diode steering element in series with a carbon storage element, the method comprising:

providing a first voltage to the nonvolatile memory cell,

such that the diode steering element is reverse biased and the carbon storage element is set to a lower resistivity state,

wherein the carbon storage element comprises a polycrystalline carbon resistivity switching material.

2. The method of claim 1 , further comprising:

providing a second voltage to the nonvolatile memory cell, such that the diode steering element is forward biased and the carbon storage element is reset to a higher resistivity state.

3. The method of claim 2 , wherein a magnitude of a second current associated with the second voltage is greater than a magnitude of a first current associated with the first voltage and the carbon storage element is set and reset a plurality of times.

4. The method of claim 1 , wherein providing the first voltage to the nonvolatile memory cell comprises providing a voltage pulse to the nonvolatile memory cell.

5. The method of claim 1 , wherein providing the first voltage to the nonvolatile memory cell comprises at least one of charging a bit line associated with the nonvolatile memory cell or discharging a capacitive storage element across the memory cell wherein the capacitive storage element comprises a capacitor driving the bit line associated with the nonvolatile memory cell.

6. The method of claim 1 , wherein:

the diode steering element comprises a p-n semiconductor diode, a p-i-n semiconductor diode, or a punch-through diode.

7. The method of claim 1 , wherein:

the carbon storage element and the diode steering element comprise a pillar shaped cell located over a lower electrode and under an upper electrode; and

the diode steering element is located over or under the carbon storage element.

8. The method of claim 2 , wherein:

when the carbon storage element is set to the lower resistivity state, conductive linkages are formed between portions of a carbon material of the carbon storage element; and

when the carbon storage element is reset to the higher resistivity state, conductive linkages are broken between the portions of the carbon material of the carbon storage element.

9. The method of claim 1 , further comprising: programming a nonvolatile memory cell array, the nonvolatile memory cell array comprising a plurality of X lines, a plurality of Y lines, and a plurality of memory cells, each memory cell comprising the diode steering element in series with the carbon storage element and each memory cell electrically connected between one of the plurality of X lines and one of the plurality of Y lines, wherein providing the first voltage comprises:

driving a selected X line of the plurality of X lines associated with at least one selected memory cell of the plurality of memory cells to a X line select voltage;

driving at least one selected Y line of the plurality of Y lines associated with the at least one selected memory cell to a Y line select voltage; wherein the X line select voltage and the Y line select voltage are configured such that the diode steering element of the at least one selected memory cell is reverse biased;

isolating the at least one selected Y line of the plurality of Y lines before the carbon storage element of the at least one selected memory cell is completely set to a lower resistivity state; and

holding the at least one selected Y line in an isolated state until the carbon storage element of the at least one selected memory cell is completely set to the lower resistivity state.

10. The method of claim 9 , wherein:

driving the selected X line to a X line select voltage, driving at least one selected Y line to the Y line select voltage, and isolating the at least one selected Y line cause an amount of charge to form on the at least one selected Y line; and

the amount of current available to completely set the carbon storage element of the at least one selected memory cell to the lower resistivity state is limited by the amount of the charge.

11. The method of claim 9 , wherein isolating the at least one selected Y line of the plurality of Y lines comprises floating the at least one selected Y line.

12. The method of claim 11 , wherein one of a plurality of MOSFETs is connected to each one of the plurality of Y lines, and floating the at least one selected Y line comprises turning off the MOSFET transistor associated with the at least one selected Y line.

13. The method of claim 12 , wherein the MOSFET transistor is a NMOS transistor isolated in a p-type semiconductor well biased at a negative well voltage that is equal to or less than a voltage applied to a source or gate of the NMOS transistor.

14. The method of claim 9 , wherein the at least one selected Y line of the plurality of Y lines is electrically connected to a data bus driven by a capacitive discharge circuit, and the data bus is isolated from a driving circuitry of the nonvolatile memory cell array.

15. The method of claim 9 , further comprising:

driving the selected X line and the at least one selected Y line such that the diode steering element of the at least one selected memory cell is forward biased and the carbon storage element of the at least one selected memory cell is reset to a higher resistivity state.

16. The method of claim 9 , wherein the diode steering element comprises a p-n semiconductor diode, a p-i-n semiconductor diode, or a punch-through diode.

17. The method of claim 9 , wherein

each of the plurality of memory cells comprises a pillar shaped cell located between one of the plurality of X lines and one of the plurality of Y lines; and

the diode steering element is located over or under the carbon storage element.

18. The method of claim 1 , further comprising:

sensing a temperature of at least one memory cell or a chip comprising the at least one memory cell, the at least one memory cell comprising the diode steering element and the carbon storage element;

selecting a setting voltage based on the sensed temperature; and

providing the first voltage comprising the setting voltage to the at least one memory cell, such that the steering element is reverse biased and the storage element is set to the lower resistivity state.

19. The method of claim 18 , further comprising providing a resetting voltage to the at least one memory cell, such that the steering element is forward biased and the storage element is reset to a higher resistivity state.

20. The method of claim 18 , wherein providing the setting voltage to the at least one memory cell comprises providing a voltage pulse to the at least one memory cell.

21. The method of claim 18 , wherein:

the sensed temperature comprises a first temperature or a second temperature;

a first setting voltage is associated with the first temperature a second setting voltage is associated with the second temperature; and

when the second temperature is lower than the first temperature, a magnitude of the second voltage is greater than a magnitude of the first voltage.

22. The method of claim 18 , wherein selecting the setting voltage based on the sensed temperature comprises increasing a magnitude of the setting voltage in a range of about 1 Volt to 2 Volts when the sensed temperature decreases, relatively, about 55 to 65 degrees Celsius.

23. The method of claim 18 , wherein selecting the setting voltage based on the sensed temperature comprises calculating the setting voltage based on an algorithm which is a function the sensed temperature or matching the sensed temperature to a setting voltage value in a look-up table.

24. The method of claim 18 , wherein the steering element comprises a p-n semiconductor diode, a p-i-n semiconductor diode, or a punch-through diode.

25. The method of claim 18 , wherein:

the storage element and the steering element comprise a pillar shaped cell located over a lower electrode and under an upper electrode;

the steering element is located over or under the storage element; and

the storage element and the steering element are electrically connected in series.

26. A method of programming a nonvolatile memory cell comprising a diode steering element in series with a carbon storage element, the method comprising:

providing a first voltage to the nonvolatile memory cell,

such that the diode steering element is reverse biased and the carbon storage element is set to a lower resistivity state,

wherein the carbon storage element comprises a graphene switchable resistance material.