IP Library Patent Application 12718939
Patent Application
App. No. 12/718,939

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF

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Quick Facts
Patent No.
US None
App. No.
12/718,939
Filed
Mar 5, 2010
Art Unit
2894
USPC
438/106
Abstract

A method of manufacture of an integrated circuit packaging system includes: forming a carrier having a cavity and a carrier top side adjacent to the cavity; mounting an integrated circuit in the cavity; forming an encapsulation surrounding the integrated circuit; and attaching a conductive channel to the carrier top side, the conductive channel over the encapsulation.

Claims (49)

1 . A method of manufacture of an integrated circuit packaging system comprising:

forming a carrier having a cavity and a carrier top side adjacent to the cavity;

mounting an integrated circuit in the cavity;

forming an encapsulation surrounding the integrated circuit; and

attaching a conductive channel to the carrier top side, the conductive channel over the encapsulation.

2 . The method as claimed in claim 1 wherein forming the encapsulation includes forming the encapsulation partially on the carrier and over the integrated circuit.

3 . The method as claimed in claim 1 further comprising grounding the conductive channel to form an electromagnetic interference shield.

4 . The method as claimed in claim 1 further comprising attaching a buffer layer on the integrated circuit.

5 . The method as claimed in claim 1 wherein:

mounting the integrated circuit includes mounting the integrated circuit having a protection liner; and

forming the encapsulation surrounding the integrated circuit includes forming the encapsulation surrounding the protection liner.

6 . A method of manufacture of an integrated circuit packaging system comprising:

forming a carrier having a cavity and a carrier top side adjacent to the cavity;

mounting an integrated circuit in the cavity;

forming an encapsulation surrounding the integrated circuit;

attaching a conductive channel to the carrier top side, the conductive channel over the encapsulation;

forming an insulation layer over the encapsulation and the conductive channel, the insulation layer having an opening; and

connecting an interconnect to the conductive channel, the interconnect over the opening.

7 . The method as claimed in claim 6 further comprising:

attaching a buffer layer on the integrated circuit; and

connecting the conductive channel to the integrated circuit through the buffer layer.

8 . The method as claimed in claim 6 wherein:

mounting the integrated circuit includes mounting the integrated circuit having a protection liner; and

further comprising:

connecting the conductive channel to the integrated circuit through the protection liner.

9 . The method as claimed in claim 6 wherein mounting the integrated circuit includes attaching an attach layer to the carrier and the integrated circuit over the carrier.

10 . The method as claimed in claim 6 wherein mounting the integrated circuit includes mounting a bumped chip in the cavity.

11 . An integrated circuit packaging system comprising:

a carrier having a cavity and a carrier top side adjacent to the cavity;

an integrated circuit in the cavity;

an encapsulation surrounding the integrated circuit; and

a conductive channel attached to the carrier top side, the conductive channel over the encapsulation.

12 . The system as claimed in claim 11 wherein the encapsulation includes the encapsulation partially on the carrier and over the integrated circuit.

13 . The system as claimed in claim 11 wherein the conductive channel is grounded to form an electromagnetic interference shield with the carrier.

14 . The system as claimed in claim 11 further comprising a buffer layer on the integrated circuit.

15 . The system as claimed in claim 11 wherein:

the integrated circuit includes the integrated circuit having a protection liner; and

the encapsulation surrounding the integrated circuit includes the encapsulation surrounding the protection liner.

16 . The system as claimed in claim 11 further comprising:

an insulation layer over the encapsulation and the conductive channel, the insulation layer having an opening; and

an interconnect connected to the conductive channel, the interconnect over the opening.

17 . The system as claimed in claim 16 further comprising:

a buffer layer on the integrated circuit; and

the conductive channel connected to the integrated circuit through the buffer layer.

18 . The system as claimed in claim 16 wherein:

the integrated circuit includes the integrated circuit having a protection liner; and

the conductive channel includes the conductive channel connected to the integrated circuit through the protection liner.

19 . The system as claimed in claim 16 further comprising an attach layer attached to the carrier and the integrated circuit over the carrier.

20 . The system as claimed in claim 16 wherein the integrated circuit includes a bumped chip in the cavity.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Jun 17, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 053476/0094 →
CHANGE OF NAME Recorded Aug 24, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 039799/0845 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 10, 2010
From: CHI, HEEJO; CHO, NAMJU; SHIN, HANGIL
To: STATS CHIPPAC LTD.
Reel/Frame 024061/0144 →