Variable read latency on a serial memory bus
View Patent ↗One or more embodiments provide a method and system of reading data from a variable-latency memory, via a serial input/output memory data interface. The system includes a memory having a variable-latency access time, a memory controller, and a serial data bus coupling the memory controller to the memory. The memory controller communicates a Read command to the memory and forces the serial data bus low for a limited time. The memory then forces the bus low and the memory controller then releases the bus. When the memory is ready to provide data, the memory provides a high signal on the serial data bus.
1. A method of reading data from a variable-latency memory, via a serial input/output memory data interface, the method comprising the steps of:
communicating a command, from a memory controller to a variable-latency memory, to read a portion of the variable-latency memory;
forcing a data line of the serial input/output memory data interface to a first logic state, for a predetermined period of time;
detecting, after the predetermined period of time, a limited duration signal on a data line of the serial input/output memory data interface, the limited duration signal detected at a second logic state; and
reading data, provided by the variable-latency memory, on the serial input/output memory data interface after an end of the limited duration signal.
2. The method of claim 1 , wherein the limited duration signal comprises a start bit.
3. The method of claim 1 , wherein the limited duration signal comprises a predetermined pattern of bits.
4. The method of claim 1 , further comprising waiting a predetermined period of time after the step of detecting the limited duration signal and the step of reading data on the serial input/output memory data interface.
5. The method of claim 1 , wherein the command includes an address of the data to read from the variable-latency memory.
6. A method of providing data from a variable-latency memory, via a serial input/output memory data interface, the method comprising the steps of:
receiving a command from a memory controller, by the variable-latency memory, to provide a portion of the variable-latency memory;
forcing a data line of the serial input/output memory data interface to a first logic state;
providing, after completion of a variable latency of the variable-latency memory, a limited duration signal on a data line of the serial input/output memory data interface, the limited duration signal provided at a second logic state; and
providing data on the serial input/output memory data interface after an end of the limited duration signal.
7. The method of claim 6 , wherein the limited duration signal comprises a start bit.
8. The method of claim 6 , wherein the limited duration signal comprises a predetermined pattern of bits.
9. The method of claim 6 , further comprising waiting a predetermined period of time after the step of providing the limited duration signal and the step of providing data on the serial input/output memory data interface.
10. The method of claim 6 , wherein the command includes an address of the data to read from the variable-latency memory.
11. A system of reading data from a variable-latency memory, via a serial input/output memory data interface, the system comprising:
a memory having a variable-latency access time;
a serial input/output memory data interface coupled at a first end to the variable latency memory; and
a memory controller coupled to a second end of the serial input/output memory data interface
wherein:
the memory Controller is configured to communicate a command to a variable latency memory to read a portion of the variable-latency memory;
the memory controller is configured to force a data line of the serial input/output memory data interface to a first logic state, for a predetermined period of time;
the variable-latency memory is configured to force the data line of the serial input/output memory data interface to a first logic state before the completion of the predetermined period of time;
the variable-latency memory is configured to provide, after completion of the variable latency access time of the variable-latency memory, a limited duration signal on a data line of the serial input/output memory interface, the limited duration signal provided at a second logic state;
the memory controller is configured to detect the limited duration signal; and
the memory controller is configured to read data, provided by the variable-latency memory, on the serial input/output memory data interface after an end of the limited duration signal.
12. A machine to read data from a variable-latency memory, via a serial input/output memory data interface, comprising:
a processor coupled to a memory,
wherein the processor is programmed to read data from the variable-latency memory by:
communicating a command, from the processor to a variable-latency memory, to read a portion of the variable-latency memory;
forcing a data line of the serial input/output memory data interface to a first logic state, for a predetermined period of time;
detecting, after the predetermined period of time, a limited duration signal on a data line of the serial input/output memory data interface, the limited duration signal detected at a second logic state; and
reading data, provided by the variable-latency memory, on the serial input/output memory data interface after an end of the limited duration signal.