IP Library Granted Patent US 7,939,928
Granted Patent B2
US 7,939,928 · App. 12/731,420 · Granted May 10, 2011

Method and apparatus for stacked die package with insulated wire bonds

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Quick Facts
Patent No.
US 7,939,928
App. No.
12/731,420
Filed
Mar 25, 2010
Granted
May 10, 2011
Kind
B2
Art Unit
2822
USPC
438/109
Abstract

A semiconductor package has a substrate with a plurality of contact pads. A first semiconductor die is mounted to the substrate. First bond wires are formed between each of the center-row contact pads of the first semiconductor die and the substrate contact pads. The first bond wires include an electrically insulative coating formed over the shaft that covers a portion of a surface of a bumped end of the first bond wires. An epoxy material is deposited over the first semiconductor die. A second semiconductor die is mounted to the epoxy material. Second bond wires are formed between each of the center-row contact pads of the second semiconductor die and the substrate contact pads. The second bond wires include an electrically insulative coating formed over the shaft of the second bond wires that covers a portion of a surface of a bumped end of the second bond wires.

Claims (53)

1. A semiconductor device, comprising:

a substrate having a plurality of contact pads formed over a first surface of the substrate;

a first semiconductor die mounted to the substrate, the first semiconductor die having center-row contact pads;

a plurality of first bond wires formed between the center-row contact pads of the first semiconductor die and the contact pads formed over the first surface of the substrate;

an epoxy material deposited over the first semiconductor die and around a portion of the first bond wires;

a second semiconductor die mounted to the epoxy material, the second semiconductor die having center-row contact pads;

a plurality of second bond wires formed between the center-row contact pads of the second semiconductor die and the contact pads formed over the first surface of the substrate;

an electrically insulative coating formed over the first bond wires and second bond wires; and

an interconnect structure formed over a second surface of the substrate opposite the first surface of the substrate.

2. The semiconductor device of claim 1 , wherein the epoxy material includes liquid dispensed epoxy or dry film epoxy.

3. The semiconductor device of claim 1 , wherein the interconnect structure includes a plurality of bumps.

4. The semiconductor device of claim 1 , wherein the first and second bond wires include an insulated gold (Au) material.

5. The semiconductor device of claim 1 , wherein the substrate includes an epoxy-based laminate, or Bismaleimide-Triazine (BT) laminate material.

6. A semiconductor device, comprising:

a substrate having a plurality of contact pads formed over a first surface of the substrate;

a first semiconductor die mounted to the substrate, the first semiconductor die having center-row contact pads;

a plurality of first bond wires formed between the center-row contact pads of the first semiconductor die and the contact pads formed over the first surface of the substrate;

an electrically insulative coating formed over the first bond wires;

an insulating material deposited over the first semiconductor die and around a portion of the first bond wires;

a second semiconductor die mounted to the insulating material; and

a plurality of second bond wires formed between contact pads of the second semiconductor die and the contact pads formed over the first surface of the substrate.

7. The semiconductor device of claim 6 , wherein the contact pads of the second semiconductor die are center-row contact pads.

8. The semiconductor device of claim 6 , wherein the insulating material includes liquid dispensed epoxy or dry film epoxy.

9. The semiconductor device of claim 6 , including an interconnect structure formed over a second surface of the substrate opposite the first surface of the substrate.

10. The semiconductor device of claim 6 , wherein the first and second bond wires include an insulated gold (Au) material.

11. The semiconductor device of claim 6 , wherein the substrate includes an epoxy-based laminate, or Bismaleimide-Triazine (BT) laminate material.

12. A semiconductor device, comprising:

a substrate having a plurality of contact pads formed over a first surface of the substrate;

a first semiconductor die mounted to the substrate, the first semiconductor die having center-row contact pads;

a plurality of first bond wires formed between the center-row contact pads of the first semiconductor die and the contact pads formed over the first surface of the substrate;

an electrically insulative coating formed over the first bond wires;

an insulating material deposited over the first semiconductor die and around a portion of the first bond wires; and

a second semiconductor die mounted to the insulating material.

13. The semiconductor device of claim 12 , including a plurality of second bond wires formed between contact pads of the second semiconductor die and the contact pads formed over the first surface of the substrate, the electrically insulative coating covering the second bond wires.

14. The semiconductor device of claim 13 , wherein the contact pads of the second semiconductor die are center-row contact pads.

15. The semiconductor device of claim 12 , wherein the insulating material includes liquid dispensed epoxy or dry film epoxy.

16. The semiconductor device of claim 12 , wherein the substrate includes an epoxy-based laminate, or Bismaleimide-Triazine (BT) laminate material.

17. The semiconductor device of claim 12 , including an interconnect structure formed over a second surface of the substrate opposite the first surface of the substrate.

18. A semiconductor device, comprising:

a substrate having a plurality of contact pads formed over a first surface of the substrate;

a first semiconductor die mounted to the substrate;

a plurality of first electrical interconnects formed between contact pads on the first semiconductor die and the contact pads formed over the first surface of the substrate;

an insulating material deposited over the first semiconductor die and around a portion of the first electrical interconnects;

a second semiconductor die mounted to the insulating material; and

a plurality of second electrical interconnects formed between contact pads formed on the second semiconductor die and the contact pads formed over the first surface of the substrate.

19. The semiconductor device of claim 18 , wherein the contact pads of the first semiconductor die are center-row contact pads.

20. The semiconductor device of claim 18 , further including:

an electrically insulative coating formed over the first electrical interconnects.

21. The semiconductor device of claim 18 , wherein the contact pads of the second semiconductor die are center-row contact pads.

22. The semiconductor device of claim 18 , wherein the first electrical interconnects and the second electrical interconnects include insulated bond wires.

23. The semiconductor device of claim 18 , wherein the insulating material includes liquid dispensed epoxy or dry film epoxy.

24. The semiconductor device of claim 18 , including an interconnect structure mounted to a second surface of the substrate opposite the first surface of the substrate.

25. The semiconductor device of claim 24 , wherein the interconnect structure includes a plurality of bumps.

Assignments (13)
NOTICE OF SUCCESSOR AGENT AND ASSIGNMENT OF SECURITY INTEREST IN REEL/FRAME 038589/0305 Recorded Nov 7, 2025
From: BANK OF AMERICA, N.A., AS PREDECESSOR AGENT
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS SUCCESSOR AGENT
Reel/Frame 073506/0385 →
MERGER Recorded Sep 26, 2024
From: MERCURY CORP. - MEMORY AND STORAGE SOLUTIONS
To: MERCURY SYSTEMS, INC.
Reel/Frame 068713/0857 →
CHANGE OF NAME Recorded Sep 26, 2024
From: MICROSEMI CORP. - MEMORY AND STORAGE SOLUTIONS
To: MERCURY CORP. - MEMORY AND STORAGE SOLUTIONS
Reel/Frame 069065/0921 →
RELEASE OF SECURITY INTEREST Recorded May 29, 2018
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MICROSEMI CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.), INC.; MICROSEMI FREQUENCY AND TIME CORPORATION; MICROSEMI COMMUNICATIONS, INC.; MICROSEMI SOC CORP.; MICROSEMI CORP. - POWER PRODUCTS GROUP; MICROSEMI CORP. - RF INTEGRATED SOLUTIONS
Reel/Frame 046251/0391 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded May 3, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MICROSEMI LLC - RF INTEGRATED SOLUTIONS; MICROSEMI CORPORATION; MICROSEMI CORP. - MEMORY AND STORAGE SOLUTIONS
Reel/Frame 038599/0667 →
SECURITY AGREEMENT Recorded May 2, 2016
From: MERCURY SYSTEMS, INC.; MERCURY DEFENSE SYSTEMS, INC.; MICROSEMI CORP.-SECURITY SOLUTIONS; MICROSEMI CORP.-MEMORY AND STORAGE SOLUTIONS
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 038589/0305 →
REGISTERED IP ASSIGNMENT AGREEMENT Recorded Apr 25, 2016
From: MICROSEMI CORPORATION
To: MICROSEMI CORP. - MEMORY AND STORAGE SOLUTIONS
Reel/Frame 038521/0378 →
PATENT SECURITY AGREEMENT Recorded Feb 3, 2016
From: MICROSEMI CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.) INC. (F/K/A LEGERITY, INC., ZARLINK SEMICONDUCTOR (V.N.) INC., CENTELLAX, INC., AND ZARLINK SEMICONDUCTOR (U.S.) INC.); MICROSEMI FREQUENCY AND TIME CORPORATION (F/K/A SYMMETRICON, INC.); MICROSEMI COMMUNICATIONS, INC. (F/K/A VITESSE SEMICONDUCTOR CORPORATION); MICROSEMI SOC CORP. (F/K/A ACTEL CORPORATION); MICROSEMI CORP. - POWER PRODUCTS GROUP (F/K/A ADVANCED POWER TECHNOLOGY INC.); MICROSEMI CORP. - RF INTEGRATED SOLUTIONS (F/K/A AML COMMUNICATIONS, INC.)
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037691/0697 →
RELEASE OF SECURITY INTEREST Recorded Jan 19, 2016
From: BANK OF AMERICA, N.A.
To: MICROSEMI CORPORATION; MICROSEMI CORP.-ANALOG MIXED SIGNAL GROUP, A DELAWARE CORPORATION; MICROSEMI SOC CORP., A CALIFORNIA CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.) INC., A DELAWARE CORPORATION; MICROSEMI FREQUENCY AND TIME CORPORATION, A DELAWARE CORPORATION; MICROSEMI COMMUNICATIONS, INC. (F/K/A VITESSE SEMICONDUCTOR CORPORATION), A DELAWARE CORPORATION; MICROSEMI CORP.-MEMORY AND STORAGE SOLUTIONS (F/K/A WHITE ELECTRONIC DESIGNS CORPORATION), AN INDIANA CORPORATION
Reel/Frame 037558/0711 →
NOTICE OF SUCCESSION OF AGENCY Recorded Apr 9, 2015
From: ROYAL BANK OF CANADA (AS SUCCESSOR TO MORGAN STANLEY & CO. LLC)
To: BANK OF AMERICA, N.A., AS SUCCESSOR AGENT
Reel/Frame 035657/0223 →
SUPPLEMENTAL PATENT SECURITY AGREEMENT Recorded Nov 11, 2011
From: MICROSEMI CORPORATION; MICROSEMI CORP. - ANALOG MIXED SIGNAL GROUP; MICROSEMI CORP. - MASSACHUSETTS; ACTEL CORPORATION
To: MORGAN STANLEY & CO. LLC
Reel/Frame 027213/0611 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2011
From: WHITE ELECTRONIC DESIGNS CORP.; ACTEL CORPORATION; MICROSEMI CORPORATION
To: MORGAN STANLEY & CO. INCORPORATED
Reel/Frame 025783/0613 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 21, 2010
From: WHITE ELECTRONIC DESIGNS CORPORATION
To: MICROSEMI CORPORATION
Reel/Frame 024710/0987 →