ULSI micro-interconnect member having ruthenium electroplating layer on barrier layer
View Patent ↗A ULSI micro-interconnect member having a substrate and a ULSI micro-interconnect formed on the substrate, wherein the ULSI micro-interconnect includes a barrier layer formed on the substrate and a ruthenium electroplating layer formed on the barrier layer; the ULSI micro-interconnect member further including a copper electroplating layer formed using the ruthenium electroplating layer as a seed layer; and a process for fabricating the ULSI micro-interconnect members.
1. A ULSI micro-interconnect member having a substrate and a ULSI micro-interconnect formed on the substrate, wherein the ULSI micro-interconnect includes at least a barrier layer formed on the substrate and a ruthenium electroplating layer formed on the barrier layer, wherein the ruthenium electroplating layer contains as an impurity not more than 100 wt. ppm of carbon.
2. The ULSI micro-interconnect member according to claim 1 , wherein a copper electroplating layer has been formed on the ruthenium electroplating layer, using the ruthenium electroplating layer as a seed layer.
3. The ULSI micro-interconnect member according to claim 1 , wherein the barrier layer of the ULSI micro-interconnect is composed of one or more metal elements selected from the group consisting of tungsten, molybdenum and niobium.
4. The ULSI micro-interconnect member according to claim 1 , wherein the substrate is a silicon substrate.
5. The ULSI micro-interconnect member according to claim 1 , wherein the ULSI micro-interconnect is a damascene copper micro-interconnect.
6. A process for fabricating a ULSI micro-interconnect, which comprises at least forming a barrier layer on a substrate and forming a ruthenium electroplating layer on the barrier layer, wherein the ruthenium electroplating layer contains as an impurity not more than 100 wt. ppm of carbon.
7. The process for fabricating a ULSI micro-interconnect according to claim 6 which further includes forming a copper electroplating layer on the ruthenium electroplating layer, using the ruthenium electroplating layer as a seed layer.
8. The process for fabricating a ULSI micro-interconnect according to claim 6 , wherein the barrier layer of the ULSI micro-interconnect is composed of one or more metal elements selected from the group consisting of tungsten, molybdenum and niobium.
9. The process for fabricating a ULSI micro-interconnect according to claim 6 , wherein the substrate is a silicon substrate.
10. The process for fabricating a ULSI micro-interconnect according to claim 6 , wherein the ULSI micro-interconnect is a damascene copper interconnect.
11. A semiconductor wafer having ULSI micro-interconnects formed by the method according to claim 6 .