Granted Patent B2

US 8,389,300 · App. 12/753,270 · Granted Mar 5, 2013

Inventors: Catherine A. Dubourdieu (New York City, NY); Martin M. Frank (Dobbs Ferry, NY)

Assignees: Centre National de la Recherche Scientifique; International Business Machines Corporation

Abstract

Claims (22)

1. A method of controlling ferroelectric characteristics of integrated circuit device components, the method comprising:

forming a ferroelectrically controllable dielectric layer over a substrate; and

forming a stress exerting structure proximate the ferroelectrically controllable dielectric layer such that a substantially uniaxial strain is induced in the ferroelectrically controllable dielectric layer by the stress exerting structure, the substantially uniaxial strain comprising a strain introduced in one direction of a surface of the ferroelectrically controllable dielectric layer;

wherein the ferroelectrically controllable dielectric layer comprises one or more of:

a ferroelectric oxide layer and a normally non-ferroelectric material layer that does not exhibit ferroelectric properties in the absence of an applied stress.

2. The method of claim 1 , wherein the ferroelectrically controllable dielectric layer comprises one or more of: BaTiO 3 , Pb[Zr x Ti 1-x ]O 3 (PZT), SrBi 2 Ta 2 O 9 (SBT), SrTiO 3 (STO), Ba 1-x Sr x TiO 3 (BST), PbTiO 3 , CaMnO 3 and BiFeO 3 .

3. The method of claim 1 , wherein the stress exerting structure comprises a different semiconductor material with respect to that of the substrate.

4. The method of claim 1 , wherein the stress exerting structure comprises a nitride layer formed over the ferroelectrically controllable dielectric layer.

5. The method of claim 4 , wherein the nitride layer is a compressive nitride layer.

6. The method of claim 4 , wherein the nitride layer is a tensile nitride layer.

7. The method of claim 1 , wherein the ferroelectrically controllable dielectric layer is included within a gate dielectric layer of a field effect transistor (FET).

8. The method of claim 7 , wherein the substrate is a silicon substrate and forming the stress exerting structure comprises growing silicon germanium source and drain regions so as to induce a compressive uniaxial strain in the ferroelectrically controllable dielectric layer.

9. The method of claim 7 , wherein the substrate is a silicon substrate and forming the stress exerting structure comprises growing carbon doped silicon source and drain regions so as to induce a tensile uniaxial strain in the ferroelectrically controllable dielectric layer.

10. The method of claim 7 , wherein forming the stress exerting structure comprises forming a compressive nitride layer over the FET.

11. The method of claim 7 , wherein forming the stress exerting structure comprises forming a tensile nitride layer over the FET.

12. The method of claim 7 , wherein the gate dielectric layer further comprises one or more additional dielectric layers.

13. The method of claim 1 , wherein the ferroelectrically controllable dielectric layer comprises a dielectric layer of a metal-insulator-metal (MIM) capacitor.

14. A method of controlling ferroelectric characteristics of integrated circuit device components, the method comprising:

forming a ferroelectrically controllable dielectric layer over a substrate; and

forming a stress exerting structure proximate the ferroelectrically controllable dielectric layer such that a substantially uniaxial strain is induced in the ferroelectrically controllable dielectric layer by the stress exerting structure;

wherein the ferroelectrically controllable dielectric layer comprises a normally non-ferroelectric material layer that does not exhibit ferroelectric properties in the absence of an applied stress.

15. The method of claim 1 , wherein the ferroelectrically controllable dielectric layer comprises one or more of: SrTiO 3 and CaMnO 3 .

Assignments (8)

Continuity (1)