Granted Patent B2

US 7,952,201 · App. 12/759,198 · Granted May 31, 2011

Abstract

Claims (65)

1. A semiconductor device comprising:

three or more semiconductor chips, each of the three or more semiconductor chips including:

a substrate having upper and lower surfaces;

first to Nth upper terminals on the upper surface, where N is an integer equal to or greater than three, the first to Nth upper terminals being arranged at vertices of a polygon;

first to Nth lower terminals on the lower surface, the first to Nth lower terminals being vertically aligned with the first to Nth upper terminals, respectively; and

first to Nth electrodes each of which penetrates the substrate to reach the upper and lower surfaces,

(1) the first to N-1th electrodes being electrically coupled to the second to Nth upper terminals, respectively,

(2) the Nth electrode being electrically coupled to the first upper terminal, and

(3) the first to Nth electrodes being electrically coupled to the first to Nth lower terminals, respectively, wherein

the three or more semiconductor chips are stacked with each other such that the first to Nth upper terminals of a lower one of the semiconductor chips are electrically coupled respectively to the first to Nth lower terminals of an upper one of the semiconductor chips, and

the first to Nth lower terminals of the lowermost semiconductor chip are electrically coupled through the first to Nth electrodes to, and vertically aligned with, the first to Nth upper terminals of the uppermost semiconductor chip, respectively.

2. The semiconductor device according to claim 1 , wherein the three or more semiconductor chips each comprise a first conductor group including the first to Nth electrodes, the first to Nth upper terminals, and the first to Nth lower electrodes, and a second conductor group including first to Mth electrodes, where M is an integer, first to Mth upper terminals, and first to Mth lower terminals.

3. The semiconductor device according to claim 2 , wherein

the first to Mth upper terminals of the second conductor group being on the upper surface of the substrate,

the first to Mth lower terminals of the second conductor group being on the lower surface of the substrate, the first to Mth lower terminals being vertically aligned with the first to Mth upper terminals, respectively; and

the first to Mth electrodes of the second conductor group, each of the first to Mth electrodes penetrates the substrate to reach the upper and lower surfaces,

(1) the first to M-1th electrodes being electrically coupled to the second to Mth upper terminals, respectively,

(2) the Mth electrode being electrically coupled to the first upper terminal, and

(3) the first to Mth electrodes being electrically coupled to the first to Mth lower terminals, respectively, wherein

the three or more semiconductor chips are stacked with each other such that the first to Mth upper terminals of a lower one of the semiconductor chips are electrically coupled respectively to the first to Mth lower terminals of an upper one of the semiconductor chips, and

the first to Mth lower terminals of the lowermost semiconductor chip are electrically coupled through the first to Mth electrodes to, and vertically aligned with, the first to Mth upper terminals of the uppermost semiconductor chip, respectively.

4. The semiconductor device according to claim 3 , wherein

M is equal to or greater than two.

5. The semiconductor device according to claim 4 , wherein N and M are coprime.

6. The semiconductor device according to claim 2 , wherein the first and second conductor groups are used for chip selection.

7. The semiconductor device according to claim 3 , wherein the first and second conductor groups are used for chip selection.

8. A semiconductor device comprising:

a plurality of semiconductor chips, each of the plurality of semiconductor chips including:

a substrate having upper and lower surfaces;

first to Nth upper terminals on the upper surface, where N is an integer equal to or greater than three, the first to Nth upper terminals being arranged at vertices of a polygon;

first to Nth lower terminals on the lower surface, the first to Nth lower terminals being vertically aligned with the first to Nth upper terminals, respectively; and

first to Nth electrodes each of which penetrates the substrate to reach the upper and lower surfaces,

(1) the first to N-1th electrodes being electrically coupled to the second to Nth upper terminals, respectively,

(2) the Nth electrode being electrically coupled to the first upper terminal, and

(3) the first to Nth electrodes being electrically coupled to the first to Nth lower terminals, respectively, wherein

the plurality of semiconductor chips are stacked with each other such that the first to Nth upper terminals of a lower one of the semiconductor chips are electrically coupled respectively to the first to Nth lower terminals of an upper one of the semiconductor chips, and

the first to Nth lower terminals of the lowermost semiconductor chip are electrically coupled through the first to Nth electrodes to, and vertically aligned with, the first to Nth upper terminals of the uppermost semiconductor chip, respectively.

9. The semiconductor device according to claim 8 , wherein the plurality of semiconductor chips each comprise a first conductor group including the first to Nth electrodes, the first to Nth upper terminals, and the first to Nth lower electrodes, and a second conductor group including first to Mth electrodes, where M is an integer, first to Mth upper terminals, and first to Mth lower terminals.

10. The semiconductor device according to claim 9 , wherein

the first to Mth upper terminals of the second conductor group being on the upper surface of the substrate,

the first to Mth lower terminals of the second conductor group being on the lower surface of the substrate, the first to Mth lower terminals being vertically aligned with the first to Mth upper terminals, respectively; and

the first to Mth electrodes of the second conductor group, each of the first to Mth electrodes penetrates the substrate to reach the upper and lower surfaces,

(1) the first to M-1th electrodes being electrically coupled to the second to Mth upper terminals, respectively,

(2) the Mth electrode being electrically coupled to the first upper terminal, and

(3) the first to Mth electrodes being electrically coupled to the first to Mth lower terminals, respectively, wherein

the three or more semiconductor chips are stacked with each other such that the first to Mth upper terminals of a lower one of the semiconductor chips are electrically coupled respectively to the first to Mth lower terminals of an upper one of the semiconductor chips, and

the first to Mth lower terminals of the lowermost semiconductor chip are electrically coupled through the first to Mth electrodes to, and vertically aligned with, the first to Mth upper terminals of the uppermost semiconductor chip, respectively.

11. The semiconductor device according to claim 10 , wherein

M is equal to or greater than two.

12. The semiconductor device according to claim 11 , wherein N and M are coprime.

13. The semiconductor device according to claim 9 , wherein the first and second conductor groups are used for chip selection.

14. The semiconductor device according to claim 10 , wherein the first and second conductor groups are used for chip selection.

15. A semiconductor device comprising:

at least first, second and third semiconductor chips, each of which comprises:

a semiconductor body including lower and upper surfaces;

at least first, second and third lower terminals provided on a side of the lower surface;

at least first, second and third upper terminals provided on a side of the upper surface, the first, second and third upper terminals being vertically aligned respectively with the first, second and third lower terminals; and

at least first, second and third conductive lines each including a connection portion penetrating the semiconductor body, each of the first, second and third conductive lines being provided to electrically connect an associated one of the first, second and third lower terminals to an associated one of the first, second, and third upper terminals which is not vertically aligned to the associated one of the lower terminals, wherein

the first, second and third semiconductor chips are stacked with each other such that the first, second and third upper terminals of a lower one of the first, second and third semiconductor chips are connected respectively to the first, second and third lower terminals of an upper one of first, second and third the semiconductor chips, and

each of the first, second and third lower terminals of a lowermost one of the first, second and third semiconductor chips is electrically connected to a corresponding one of the first, second and third upper terminals of an uppermost one of the first, second and third semiconductor chips which are vertically aligned respectively with the first, second and third lower electrodes of the lowermost one of the first, second and third semiconductor chips.

16. The device as claimed in claim 15 , wherein each of the first, second and third conductive lines further includes an interconnection line provided between the connection portion and an associated one of the first, second and third upper terminals to electrically connect the associated one of the first, second and third lower terminals to the associated one of the first, second and third upper terminals which is not vertically aligned to the associated one of the first, second and third lower terminals.

17. The device as claimed in claim 15 , wherein the first, second and third upper terminals are arranged at vertices of a polygon.

18. The device as claimed in claim 15 , wherein the connection portions of the first, second and third conductive lines are vertically aligned respectively with the first, second and third lower terminals and with the first, second and third upper terminals, and the connection portions of the first, second and third conductive lines are connected respectively with the first, second and third lower terminals.

19. The device as claimed in claim 18 , wherein each of the first, second and third conductive lines further includes an interconnection line provided between the connection portion and an associated one of the first, second and third upper terminals to electrically connect the associated one of the first, second and third lower terminals to the associated one of the first, second and third upper terminals which is not vertically aligned to the associated one of the lower terminals.

20. The device as claimed in claim 18 , wherein the first, second and third upper terminals are arranged at vertices of a polygon.

Assignments (7)