Granted Patent B2

US 7,867,848 · App. 12/765,646 · Granted Jan 11, 2011

Abstract

Claims (41)

1. A method for fabricating a dual bit memory device, the method comprising:

fabricating a charge trapping stack overlying a substrate, wherein the charge trapping stack comprises a tunnel oxide layer, a charge trapping layer overlying the tunnel oxide layer, and an insulating layer overlying the charge trapping layer;

forming a plurality of sacrificial members overlying the charge trapping layer;

etching isolation openings within the charge trapping layer between adjacent sacrificial members of the plurality of sacrificial members;

globally depositing an oxide layer overlying the plurality of sacrificial members, within the isolation openings, and overlying portions of the charge trapping layer;

forming a plurality of control gates overlying each of the isolation openings;

removing the plurality of sacrificial members;

etching portions of the oxide layer and the charge trapping layer that do not underlie the plurality of control gates; and

forming a plurality of impurity doped bitline regions within the substrate using the plurality of control gates as a mask.

2. The method of claim 1 , wherein the step of forming a plurality of sacrificial members overlying the charge trapping layer comprises the steps of:

depositing an intermediate layer overlying the charge trapping layer;

depositing a sacrificial layer overlying the intermediate layer;

removing a portion of the sacrificial layer to form the plurality of sacrificial members; and

removing portions of the intermediate layer that do not underlie the sacrificial members.

3. The method of claim 2 , further comprising the step of forming sidewall spacers about sidewalls of each of the plurality of sacrificial members after the step of forming a plurality of sacrificial members overlying the charge trapping layer.

4. The method of claim 3 , wherein the step of forming sidewall spacers comprises the step of forming sidewall spacers of a material that is different from the sacrificial layer and the insulating layer.

5. The method of claim 4 , wherein the step of etching isolation openings within the charge trapping layer between adjacent sacrificial members of the plurality of sacrificial members comprises the step of etching the isolation openings using the sacrificial members and the sidewall spacers as a mask.

6. A method for fabricating a flash memory device, the method comprising:

fabricating a charge trapping stack overlying a silicon substrate, wherein the charge trapping stack comprises a first dielectric layer, a charge trapping layer overlying the first dielectric layer, and a second dielectric layer overlying the charge trapping layer;

depositing an intermediate layer overlying the second dielectric layer;

depositing a sacrificial layer overlying the intermediate layer;

removing portions of the sacrificial layer to form a plurality of sacrificial members;

etching the intermediate layer to expose portions of the second dielectric layer that do not underlie the sacrificial members;

etching isolation openings through the second dielectric layer and the charge trapping layer using the sacrificial members as a mask;

depositing a first insulating material overlying the sacrificial members and within the isolation openings;

fabricating control gates between adjacent sacrificial members of the plurality of sacrificial members;

removing the sacrificial members;

removing the intermediate layer;

etching the first insulating material and the charge trapping layer using the control gates as a mask; and

forming impurity doped bitline regions within the substrate using the control gates as an implantation mask.

7. The method of claim 6 , further comprising the steps of:

conformally depositing a second insulating material layer overlying the control gates and the impurity doped bitline regions; and

etching the insulating material layer to form bitline spacers between adjacent control gates.

8. The method of claim 6 , further comprising the step of forming sidewall spacers about the sidewalls of each of the plurality of sacrificial members after the step of etching the intermediate layer to expose portions of the second dielectric layer that do not underlie the sacrificial members, and wherein the step of etching isolation openings through the second dielectric layer and the charge trapping layer using the sacrificial members as a mask comprises the step of etching the isolation openings using the sacrificial members and the sidewall spacers as a mask.

9. The method of claim 6 , wherein the step of fabricating a charge trapping stack overlying a silicon substrate comprises the steps of depositing a first silicon oxide layer overlying the substrate, a silicon-rich silicon nitride layer overlying the first silicon oxide layer, and a second silicon oxide layer overlying the silicon-rich silicon nitride layer.

10. The method of claim 3 , wherein the step of forming sidewall spacers comprises the step of forming sidewall spacers of silicon nitride.

11. The method of claim 8 , wherein the step of forming sidewall spacers comprises the step of forming sidewall spacers of silicon nitride.

12. The method of claim 2 , wherein the step of depositing an intermediate layer comprises depositing a polycrystalline silicon layer.

13. The method of claim 2 , wherein the step of depositing a sacrificial layer comprises depositing a silicon oxide layer.

14. The method of claim 6 , wherein the step of depositing an intermediate layer comprises depositing a polycrystalline silicon layer.

15. The method of claim 6 , wherein the step of depositing a sacrificial layer comprises depositing a silicon oxide layer.

Assignments (6)