IP Library Granted Patent US 7,919,393
Granted Patent B2
US 7,919,393 · App. 12/769,299 · Granted Apr 5, 2011

Forming structures that include a relaxed or pseudo-relaxed layer on a substrate

Assignee: S.O.I.Tec Silicon on Insulator Technologies
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Quick Facts
Patent No.
US 7,919,393
App. No.
12/769,299
Granted
Apr 5, 2011
Kind
B2
Abstract

A method for forming a structure that includes a relaxed or pseudo-relaxed layer on a substrate. The method includes the steps of growing an elastically stressed layer of semiconductor material on a donor substrate; forming a glassy layer of a viscous material on the stressed layer; removing a portion of the donor substrate to form a structure that includes the glassy layer, the stressed layer and a surface layer of donor substrate material; patterning the stressed layer; and heat treating the structure at a temperature of at least a viscosity temperature of the glassy layer to relax the stressed layer and form the relaxed or pseudo-relaxed layer of the structure.

Claims (25)

1. A method of forming a structure that includes a relaxed or pseudo-relaxed layer on a substrate which comprises:

growing an elastically stressed layer of semiconductor material on a donor substrate;

forming a glassy layer of a viscous material on the stressed layer;

removing a portion of the donor substrate to form a structure that includes the glassy layer, the stressed layer and a surface layer of donor substrate material;

patterning the stressed layer; and

heat treating the structure at a temperature of at least a viscosity temperature of the glassy layer to relax the stressed layer and form the relaxed or pseudo-relaxed layer of the structure.

2. The method of claim 1 , wherein the patterning comprises etching islands in the stressed layer to contribute to relaxation of the stressed layer during the heat treating.

3. The method of claim 2 , which further comprises forming components on the islands.

4. The method of claim 3 , wherein the components are formed after forming the relaxed or pseudo-relaxed layer.

5. The method of claim 3 , wherein the components are formed during or in continuity with the heat treating.

6. The method of claim 1 , which further comprises applying an epitaxial growth process to provide at least one epitaxial layer on the structure.

7. The method of claim 6 , wherein the surface layer is removed before providing at least one epitaxial layer on the structure.

8. The method of claim 7 , wherein the epitaxial growth process provides at least one epitaxial layer by applying one or more of a SiGe or SiGeC layer, or of a stressed Si or SiC layer, or successive epitaxial growths of SiGe or SiGeC layers or of alternately stressed Si or SiC layers in order to form a multilayer structure.

9. The method of claim 8 , which further comprises applying one or more finishing treatments to the multilayer structure to improve properties.

10. The method of claim 6 , which further comprises forming components on the structure.

11. The method of claim 10 , wherein the components are applied to the structure upon the stressed layer, the relaxed or pseudo-relaxed layer, or upon the epitaxial layer.

12. The method of claim 1 , wherein the stressed layer is material of Groups III-V or II-VI.

13. The method of claim 1 , wherein the material of the surface layer becomes viscous at a certain viscosity temperature of above about 900° C.

14. The method of claim 1 , which further comprises bonding a receiver substrate to the structure to form a second structure before removing part of the donor substrate, the second structure comprising the receiver substrate, the relaxed or pseudo-relaxed layer, the glassy layer and the surface layer.

15. The method of claim 14 , wherein the glassy layer is formed on the receiving substrate prior to bonding with the stressed layer.

16. The method of claim 14 , which further comprises applying a bonding layer onto at least one of the patterned layer or the receiver substrate prior to bonding.

17. The method of claim 16 , wherein the bonding layer comprises silicon oxide.

18. The method of claim 14 , which further comprises providing a zone of weakness in the donor substrate so that the donor substrate can be removed by detaching along the zone of weakness.

19. The method of claim 18 , wherein the donor substrate is fabricated by forming a porous layer on a crystalline carrier substrate and growing a crystalline layer on the porous layer, such that the porous layer comprises the zone of weakness of the donor substrate, and further wherein the donor substrate is detached along the weakened zone by at least one of chemical etching or mechano-chemical etching.

20. The method of claim 18 , wherein the zone of weakness is formed by implanting atomic species in the donor substrate and the donor substrate is detached along the weakened zone by applying thermal or mechanical energy.

Assignments (2)
CHANGE OF NAME Recorded Mar 1, 2012
From: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
To: SOITEC
Reel/Frame 027793/0535 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 28, 2012
From: GHYSELEN, BRUNO; MAZURE, CARLOS; ARENE, EMMANUEL
To: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
Reel/Frame 027772/0620 →
Priority Claims (1)
FR 03 02518 · Feb 28, 2003 · national
Continuity (4)
Continuation 11345495 · Feb 2, 2006
Continuation 10784016 · Feb 20, 2004
Provisional Application 60483476 · Jun 26, 2003
Related Publication 20100210090A1 · Aug 19, 2010