TEST METHOD, TEST CONTROL PROGRAM AND SEMICONDUCTOR DEVICE
In a method of performing a test on a logic circuit in accordance with an exemplary aspect of the present invention, the test is performed by supplying a clock signal from a clock supply circuit to a plurality of clock domains operating by a clock signal of a same frequency. The method includes calculating a number of test patterns of each of the plurality of internal clock domains; classifying the plurality of clock domains into a plurality of groups based on the calculated number of test patterns; and assigning a clock supply circuit independently to each of the groups into which the clock domains are classified.
1 . A method of performing a test on a logic circuit, the test being performed by supplying a clock signal from a clock supply circuit to a plurality of clock domains operating by a clock signal of a same frequency, the method comprising:
calculating a number of test patterns of each of the plurality of clock domains;
classifying the plurality of clock domains into a plurality of groups based on the calculated number of test patterns; and
assigning a clock supply circuit independently to each of the groups into which the clock domains are classified.
2 . The method of performing a test on a logic circuit according to claim 1 , wherein
the plurality of clock domains are classified into the plurality of groups so that the numbers of test patterns get closer to each other.
3 . The method of performing a test on a logic circuit according to claim 2 , wherein
the plurality of clock domains are classified into the groups in a descending order of the calculated number of test patterns for the clock domains.
4 . The method of performing a test on a logic circuit according to claim 3 , further comprising:
selecting a group having the smallest number of test patterns; and
classifying the clock domain into the selected group.
5 . The method of performing a test on a logic circuit according to claim 1 , wherein
the number of test patterns is calculated for each subgroup including the clock domain having no data-path dependency relation; and
the subgroup is classified into the groups based on the calculated number of test patterns.
6 . The method of performing a test on a logic circuit according to claim 1 , wherein
the number of the clock supply circuits to be assigned is determined according to the number of terminals for supplying a clock signal to the clock supply circuit that can be added.
7 . The method of performing a test on a logic circuit according to claim 1 , wherein
the number of test patterns are calculated based on a number of flip flop circuits included in the clock domain.
8 . A non-transitory computer readable medium storing a program for causing a computer to perform a test on a logic circuit by supplying a clock signal from a clock supply circuit to a plurality of clock domains operating with a clock signal of a same frequency, the program causing to the computer to:
calculate a number of test patterns of each of the plurality of clock domains;
classify the plurality of clock domains into a plurality of groups based on the calculated number of test patterns;
assign a clock supply circuit independently to each of the groups into which the clock domains are classified;
supply the clock signal from the clock supply circuit to the groups into which the clock domain is classified.
9 . The non-transitory computer readable medium that stores a program according to claim 8 , wherein
the plurality of clock domains are classified into the plurality of groups so that the numbers of test patterns get closer to each other.
10 . The non-transitory computer readable medium that stores a program according to claim 9 , wherein
the plurality of clock domains are classified into the groups in a descending order of the calculated number of test patterns for the clock domains.
11 . The non-transitory computer readable medium that stores a program according to claim 10 , further comprising:
select a group having the smallest number of test patterns; and
classify the clock domain into the selected group.
12 . A semiconductor device including a first clock domain and a second clock domain operating with a clock signal of a same frequency comprising:
a first clock supply circuit that supplies a test clock to the first clock domain;
a second clock supply circuit that supplies a test clock to the second clock domain;
a first terminal that inputs a test clock to the first clock supply circuit; and
a second terminal that inputs a test clock to the second clock supply circuit.