IP Library Granted Patent US 9,029,193
Granted Patent B2
US 9,029,193 · App. 12/775,170 · Granted May 12, 2015

Semiconductor device and method of forming an interconnect structure for 3-D devices using encapsulant for structural support

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Quick Facts
Patent No.
US 9,029,193
App. No.
12/775,170
Granted
May 12, 2015
Kind
B2
Abstract

A semiconductor device has a first interconnect structure formed over a first side of a substrate. A semiconductor die is mounted to the first interconnect structure. An encapsulant is deposited over the semiconductor die and first interconnect structure for structural support. A portion of a second side of the substrate, opposite the first side of the substrate, is removed to reduce its thickness. The encapsulant maintains substrate robustness during thinning process. A TSV is formed through the second side of the substrate to the first interconnect structure. A second interconnect structure is formed in the TSV. The TSV has a first insulating layer formed over the second side of the substrate and first conductive layer formed over the first insulating layer and into the TSV. The second interconnect structure has a second conductive layer formed over the first conductive layer in an area away from the TSV.

Claims (81)

1. A method of making a semiconductor device, comprising:

providing a substrate;

forming a first interconnect structure, including a plurality of conductive pillars, over a first surface of the substrate;

disposing a semiconductor die over the first interconnect structure with bumps electrically connected to the conductive pillars;

depositing an encapsulant over the semiconductor die and first interconnect structure;

forming a via through a second surface of the substrate, opposite the first surface of the substrate, to the first interconnect structure; and

forming a second interconnect structure in the via.

2. The method of claim 1 , wherein forming the second interconnect structure includes:

applying an insulating layer over a sidewall of the via; and

forming a conductive layer over the insulating layer in the via.

3. The method of claim 1 , wherein the via includes a tapered sidewall.

4. The method of claim 1 , wherein forming the first interconnect structure includes:

forming a first conductive layer over the first surface of the substrate;

forming a first insulating layer over the first conductive layer and substrate;

forming a second conductive layer over the first insulating layer and first conductive layer;

forming a second insulating layer over the second conductive layer and first insulating layer;

forming a conductive pillar over the second conductive layer;

forming a third insulating layer around the conductive pillar; and

forming a third conductive layer over the conductive pillar and electrically connecting the third conductive layer to the semiconductor die.

5. The method of claim 1 , wherein forming the second interconnect structure further includes forming a bump in the via over the first interconnect structure.

6. The method of claim 1 , further including mounting the semiconductor device to a printed circuit board through the second interconnect structure.

7. The method of claim 1 , wherein forming the second interconnect structure includes:

forming an insulating layer over the first interconnect structure; and

forming a bump over the first interconnect structure.

8. A method of making a semiconductor device, comprising:

providing a substrate;

forming a first interconnect structure, including a plurality of conductive pillars, over a first surface of the substrate;

disposing a semiconductor die over the first interconnect structure with bumps electrically connected to the conductive pillars;

depositing an encapsulant over the semiconductor die and first interconnect structure;

forming a via through a second surface of the substrate, opposite the first surface of the substrate, to the first interconnect structure; and

forming a first conductive layer in the via.

9. The method of claim 8 , further including forming a second interconnect structure over the first conductive layer.

10. The method of claim 9 , wherein forming the second interconnect structure includes forming a bump in the via over the first conductive layer.

11. The method of claim 8 , wherein the via includes a tapered sidewall.

12. The method of claim 8 , further including removing a portion of the substrate to reduce a thickness of the substrate.

13. The method of claim 8 , wherein forming the first interconnect structure includes:

forming a second conductive layer over the first surface of the substrate;

forming a first insulating layer over the second conductive layer and substrate;

forming a third conductive layer over the first insulating layer and second conductive layer;

forming a second insulating layer over the third conductive layer and first insulating layer;

forming a conductive pillar over the third conductive layer;

forming a third insulating layer around the conductive pillar; and

forming a fourth conductive layer over the conductive pillar and electrically connecting the third conductive layer to the semiconductor die.

14. The method of claim 8 , further including forming an insulating layer over a sidewall of the via.

15. A method of making a semiconductor device, comprising:

providing a substrate;

forming a first interconnect structure, including a plurality of conductive pillars, over a first surface of the substrate;

disposing a semiconductor die over the first interconnect structure;

depositing an encapsulant over the semiconductor die and first interconnect structure;

forming a via through a second surface of the substrate, opposite the first surface of the substrate, to the first interconnect structure; and

forming a first conductive layer over a sidewall of the via.

16. The method of claim 15 , further including forming an insulating layer over the sidewall of the via.

17. The method of claim 15 , further including forming a second interconnect structure over the first conductive layer.

18. The method of claim 17 , wherein forming the second interconnect structure includes forming a bump in the via over the first conductive layer.

19. The method of claim 15 , further including removing a portion of the substrate to reduce a thickness of the substrate.

20. The method of claim 15 , wherein forming the first interconnect structure includes:

forming a second conductive layer over the first surface of the substrate;

forming a first insulating layer over the second conductive layer and substrate;

forming a third conductive layer over the first insulating layer and second conductive layer;

forming a second insulating layer over the third conductive layer and first insulating layer;

forming a conductive pillar over the third conductive layer;

forming a third insulating layer around the conductive pillar; and

forming a fourth conductive layer over the conductive pillar and electrically connecting the fourth conductive layer to the semiconductor die.

21. A method of making a semiconductor device, comprising:

providing a substrate;

forming a first interconnect structure over a first surface of the substrate;

disposing a semiconductor die over the first interconnect structure;

depositing an encapsulant over the semiconductor die and extending to the substrate;

forming an opening in the substrate extending to the first interconnect structure; and

forming a second interconnect structure over the substrate and into the opening in the substrate to contact the first interconnect structure.

22. The method of claim 21 , wherein forming the first interconnect structure includes:

forming a first conductive layer over the first surface of the substrate;

forming a first insulating layer over the first conductive layer and substrate;

forming a second conductive layer over the first insulating layer and first conductive layer;

forming a second insulating layer over the second conductive layer and first insulating layer;

forming a conductive pillar over the second conductive layer;

forming a third insulating layer around the conductive pillar; and

forming a third conductive layer over the conductive pillar and electrically connecting the third conductive layer to the semiconductor die.

23. The method of claim 21 , wherein forming the second interconnect structure includes:

forming an insulating layer over the first interconnect structure; and

forming a bump over the first interconnect structure.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY NAME ON THE COVER SHEET PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0145. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 5, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2019
From: STATS CHIPPAC PTE. LTD.
To: JCET SEMICONDUCTOR (SHAOXING) CO., LTD.
Reel/Frame 051365/0680 →
RELEASE OF SECURITY INTEREST Recorded Dec 13, 2019
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 051285/0318 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →