Electrically tunable continuous-time circuit and method for compensating a polynomial voltage-dependent characteristic of capacitance
View Patent ↗A capacitance compensation circuit includes an input terminal, a plurality of switches coupled to the input terminal, a plurality of varactors coupled to the plurality of switches, and a plurality of blocking capacitors coupled between the plurality of switches and the plurality of varactors. The capacitance compensation circuit further includes a plurality of adjustable biasing circuits to precisely compensate for linear and parabolic voltage dependent components of an input or other capacitor. Two such circuits can be used with a single input terminal to compensate for both increasing and decreasing voltage dependent characteristics of a target capacitor.
1. A capacitance compensation circuit comprising:
an input terminal;
a circuit to compensate for input capacitance increasing against the input terminal voltage, comprising a first plurality of switches coupled to the input terminal, a first plurality of blocking capacitors coupled to the first plurality of switches, and a first plurality of varactors coupled to the plurality of blocking capacitors; and
a circuit to compensate for input capacitance decreasing against the input terminal voltage, comprising a second plurality of switches coupled to the input terminal, a second plurality of blocking capacitors coupled to the second plurality of switches, and a second plurality of varactors coupled to the second plurality of blocking capacitors.
2. The capacitance compensation circuit of claim 1 wherein the first plurality of switches comprises a plurality of devices inactivated by a switching voltage thereof exceeding a threshold voltage.
3. The capacitance compensation circuit of claim 1 wherein the second plurality of switches comprises a plurality of devices activated by a switching voltage thereof exceeding a threshold voltage.
4. The capacitance compensation circuit of claim 1 further comprising: a first plurality of bias levels coupled to a plurality of control terminals associated with the first plurality of switches; and
a second plurality of bias levels coupled to a plurality of control terminals associated with the second plurality of switches.
5. The capacitance compensation circuit of claim 4 wherein:
the first plurality of bias levels comprises a first plurality of constant bias levels; and
the second plurality of bias levels comprises a second plurality of constant bias levels.
6. The capacitance compensation circuit of claim 1 further comprising:
a first plurality of bias devices coupled to the first plurality of blocking capacitors; and
a second plurality of bias devices coupled to the second plurality of blocking capacitors.
7. The capacitance compensation circuit of claim 6 further comprising:
a first adjustable source coupled to the first plurality of bias devices; and
a second adjustable source coupled to the second plurality of bias devices.
8. The capacitance compensation circuit of claim 1 further comprising:
a first plurality of adjustable bias levels coupled to the first plurality of varactors; and
a second plurality of adjustable bias levels coupled to the second plurality of varactors.
9. The capacitance non-linearity compensation circuit of claim 8 further comprising:
a first adjustable bias source to similarly adjust the capacitance of each varactor in the first plurality of varactors; and
a second adjustable bias source to similarly adjust the capacitance of each varactor in the second plurality of varactors.
10. The capacitance non-linearity compensation circuit of claim 8 further comprising:
a first adjustable bias source to linearly adjust the capacitance of consecutive varactors in the first plurality of varactors; and
a second adjustable bias source to linearly adjust the capacitance of consecutive varactors in the second plurality of varactors.
11. The capacitance compensation circuit of claim 1 wherein the first and second plurality of varactors each comprise a plurality of MOS varactors.
12. The capacitance compensation circuit of claim 1 wherein the first and second plurality of varactors each comprise a plurality of p-n junction varactors.