Embedded magnetic random access memory (MRAM)
View Patent ↗A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed therethrough and are formed on top of the access transistor. An magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ.
1. A method of manufacturing a magnetic random access memory (MRAM) cell comprising:
forming a plurality of diffusion regions and a transistor gate, collectively defining an access transistor, in a silicon substrate;
forming a first metal-interposed-in-interlayer dielectric (ILD) layer having a first metal dispersed therethrough on top of the access transistor, the first metal coupled to one of the plurality of diffusion regions and being in close proximity to a bit line;
forming a plurality of ILD layers on top of the first ILD layer with each layer being formed on top of a previous layer;
forming a magneto tunnel junction (MTJ) substantially on top of the plurality of ILD layers, each of the plurality of ILD layers having the metal dispersed therethrough;
forming a MTJ mask on top of the MTJ for patterning the MTJ;
etching the MTJ mask to expose the MTJ;
forming a spacer on top of and around the exposed MTJ;
depositing a second metal on top of the bit line and over a portion of the top most one of the plurality of ILD layers and extending over the top of the MTJ;
forming an interconnect mask on top of the second metal defining an interconnect;
depositing at least one passivation layer on top of the MTJ and the surface of the top most layer of the plurality of ILD layers and the bit line;
masking and etching the at least one passivation layer; and
removing the interconnect to expose the MTJ thereby forming an embedded magnetic random access memory (MRAM).
2. The method of manufacturing a magnetic random access memory (MRAM) cell, as recited in claim 1 , wherein the spacer is made of silicon nitride.
3. The method of manufacturing a magnetic random access memory (MRAM) cell, as recited in claim 1 , wherein the spacer is approximately 1,500 Angstroms in thickness.
4. The method of manufacturing a magnetic random access memory (MRAM) cell, as recited in claim 1 , wherein the spacer is made of oxide.
5. The method of manufacturing a magnetic random access memory (MRAM) cell, as recited in claim 1 , wherein the MTJ is offset from the first metal.
6. The method of manufacturing a magnetic random access memory (MRAM) cell, as recited in claim 1 , wherein more than one embedded MRAM is formed on the silicon substrate.
7. The method of manufacturing a magnetic random access memory (MRAM) cell, as recited in claim 1 , wherein the first and plurality of ILD layers are made using a double damascene process.
8. The method of manufacturing a magnetic random access memory (MRAM) cell, as recited in claim 1 , wherein the plurality of ILD layers is made using a double damascene process.