IP Library Granted Patent US 8,205,017
Granted Patent B2
US 8,205,017 · App. 12/785,666 · Granted Jun 19, 2012

Systems and methods for addressing and synchronizing multiple devices

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Quick Facts
Patent No.
US 8,205,017
App. No.
12/785,666
Granted
Jun 19, 2012
Kind
B2
Abstract

This is generally directed to systems and methods for control of two or more devices through a shared control bus. For example, the devices can be coupled to a host system through the control bus. In some embodiments, the devices can be configured by the host system through address select pins of the devices. For example, the host system can sequentially program each device to change its default address to a unique address. In some embodiments, an event can be propagated through each device, thus resulting in each device receiving the event at a different time. In some embodiments, configuration by the host system can include programming each device with a value representing its own position in the chain. In this case, a device can use this value to delay its response to the event, thereby allowing all the devices in the chain to respond to the event simultaneously.

Claims (47)

1. A method for assigning a unique address to each device of a plurality of devices configured in a chain, the method comprising:

transmitting a first command including an address ID of a first default address, wherein the first command comprises instructions to assign a first unique address, and wherein only a first device of the chain is initially assigned the first default address and each of the remaining devices of the chain is initially assigned a second default address, such that only the first device of the chain responds to the first command;

transmitting a second command including the first unique address, wherein the second command comprises instructions to invert a logic level on an output pin, and wherein only the first device responds to the second command;

receiving the logic level from the output pin of the first device on an input pin of a second device, wherein inversion of the logic level causes the second device to change behavior from ignoring the first default address to responding to the first default address; and

transmitting a third command including the first default address, wherein the third command comprises instructions to assign a second unique address, and wherein only the second device of the chain is assigned the first default address, the first device of the chain is assigned the first unique address, and each of the other devices of the chain is assigned the second default address, such that only the second device of the chain responds to the third command.

2. The method of claim 1 , wherein the instructions to invert a logic level comprise:

instructions to output a logic low signal on the output pin.

3. The method of claim 1 , wherein receiving comprises:

changing an address ID of the second device from the second default address to the first default address in response to the receiving.

4. The method of claim 1 , wherein the input pin of the second device comprises an address select pin.

5. The method of claim 1 , wherein:

the first device is hardwired such that the first device is initially assigned the first default address; and

the first device responds to the first command in response to its hardwired, first default address matching the address ID included in the first command.

6. The method of claim 1 , wherein the first device responding to the first command comprises:

writing to an address_register of the first device to change an address associated with the first device to the first unique address.

7. The method of claim 1 , wherein transmitting the first command, transmitting the second command, and transmitting the third command is performed by a host system external to the plurality of devices.

8. The method of claim 1 , wherein:

the plurality of devices are all sequentially configured by repeating the two steps of:

transmitting a first command; and

transmitting a second command;

each time the two steps are repeated a new unique ID is used in the two steps; and

the two steps are repeated until each device in the plurality of devices has been configured by the two steps.

9. The method of claim 1 , wherein the first command and the second command comprise a single command that is transmitted at the same time.

10. The method of claim 1 , wherein the first, second, and third commands are transmitted to the plurality of devices using an inter-integrated circuit (I2C) bus configuration.

11. The method of claim 1 , wherein the plurality of devices are further configured in an inter-integrated circuit (I2C) bus configuration.

12. The method of claim 1 , wherein the output pin instructed to output the logic low signal by the second command comprises a Test Mode Select pin of the first device.

13. The method of claim 1 , wherein the second command further includes instructions to:

enable a master device position;

enable a chain configuration; and

enable a multi-sync function.

14. The method of claim 1 , wherein:

in response to the first device responding to the second command, an address ID of the first device is not affected by a logic level received at an address select pin of the first device, such that the address ID of the first device subsequently remains as the first unique address.

15. A method for sequentially configuring each device in a daisy-chain of devices, wherein each device is electrically coupled to the other devices in the daisy-chain, the method comprising:

transmitting, from a host system external to the daisy-chain, a first command that is addressed to a first default address, wherein the first command comprises instructions to assign a new, unique address to a single, particular device, wherein the particular device is initially assigned the first default address and each of the remaining devices of the chain is initially assigned a second default address, such that only the particular device responds to the first default address;

transmitting, from the host system, a second command that is addressed to the new, unique address, wherein the particular device is assigned the new, unique address and now responds to the new, unique address and wherein the second command comprises instructions to:

define a position of the particular device in the daisy-chain;

configure a particular pin of the particular device as an output pin, wherein the particular pin is electrically coupled to an address select pin of a next device in the daisy chain; and

invert a logic level of the particular pin; and

repeating the transmitting of the first command and the transmitting of the second command until each device in the second chain has been configured by the first and second command, and wherein a different, unique address is used each time the transmitting is repeated.

16. The method of claim 15 , wherein:

the host system is coupled to each device in the daisy chain through a two-wire control bus; and

the transmitting comprises transmitting on a serial data line of the two-wire control bus.

17. The method of claim 15 , wherein defining position comprises:

defining a number of the devices in the daisy-chain prior to transmitting the first and second commands; and

decrementing the number each time the transmitting of the first command and the second command is repeated to define the position.

18. The method of claim 15 , wherein defining the position comprises:

automatically determining a number of the devices in the daisy-chain as the transmitting of the first command and the second command is repeated.

Assignments (5)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 23, 2014
From: APTINA IMAGING CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 034037/0711 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 24, 2010
From: PARR, IAN; CROOK, NEAL
To: APTINA IMAGING CORPORATION
Reel/Frame 024428/0952 →