IP Library Granted Patent US 8,390,310
Granted Patent B2
US 8,390,310 · App. 12/801,207 · Granted Mar 5, 2013

Test system and test method of semiconductor integrated circuit

Inventor: Shinsuke Hamanaka (Kanagawa, JP)
Assignee: Renesas Electronics Corporation
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Quick Facts
Patent No.
US 8,390,310
App. No.
12/801,207
Granted
Mar 5, 2013
Kind
B2
Abstract

Provided is a test system of a semiconductor integrated circuit including an output device and an input device for conducting an input/output characteristics test of the output device and the input device inside the semiconductor integrated circuit. In the system, a transmission line provided in a test board where the semiconductor integrated circuit is mounted on establishes a wired connection between an external terminal of one circuit of one of the output device and the input device and external terminals of a plurality of circuits of another one of the output device and the input device.

Claims (15)

1. A test system of a semiconductor integrated circuit comprising an output device and an input device for conducting an input/output characteristics test of the output device and the input device inside the semiconductor integrated circuit, the test system comprising:

a test board where the semiconductor integrated circuit is mounted on; and

a transmission line that is provided in the test board and that establishes a wired connection between an external terminal of one circuit of one of the output device and the input device and external terminals of a plurality of circuits of another one of the output device and the input device,

wherein the transmission line comprises a plurality of selection switches that are connected between the external terminal of one circuit of said one of the output device and the input device and the external terminals of the plurality of circuits of said another one of the output device and the input device, and that are controlled so that, when at least one selection switch is in an on-state, other selection switches are in an off-state.

2. The test system according to claim 1 , wherein the plurality of circuits of said another one of the output device and the input device have a function of enabling or disabling a signal output or a signal input, and are controlled so that, when at least one of the plurality of circuits of said another one of the output device and, the input device is enabled, other circuits are disabled.

3. A test system of a semiconductor integrated circuit comprising an output device and an input device for conducting an input/output characteristics test of the output device and the input device inside the semiconductor integrated circuit, the test system comprising:

a test board where the semiconductor integrated circuit is mounted on; and

a transmission line that is provided in the test board and that establishes a wired connection between an external terminal of one circuit of one of the output device and the input device and external terminals of a plurality of circuits of another one of the output device and the input device,

wherein the transmission line comprises a coupling capacitor connected between the external terminal of one circuit of said one of the output device and the input device and the external terminals of the plurality of circuits of said another one of the output device and the input device.

4. The test system according to claim 3 , wherein a plurality of circuits of the input device comprise terminating resistors respectively connected to the external terminals, and the terminating resistors have a function of turning on or off as resistors and are controlled so that, when at least one resistor is in an on-state, other resistors are in an off state.

5. The test system according to claim 4 , wherein the semiconductor integrated circuit comprises:

a test pattern generation circuit that generates a test pattern of a transmission signal to be transmitted from one circuit of the output device; and

a check circuit that checks a test pattern regenerated by the plurality of circuits of the input device based on the transmission signal from the output device, and

the check circuit checks the test pattern regenerated by the input device comprising the terminating resistor in an on-state among the plurality of circuits of the input device.

6. The test system according to claim 4 , wherein the terminating resistors comprise variable resistors and are adjustable to have a resistance value corresponding to characteristics of the transmission line during an on-state.

Assignments (3)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
CHANGE OF NAME Recorded Oct 26, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025191/0985 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2010
From: HAMANAKA, SHINSUKE
To: NEC ELECTRONICS CORPORATION
Reel/Frame 024490/0803 →
Priority Claims (1)
JP 2009-133162 · Jun 2, 2009 · national
Continuity (1)
Related Publication 20100301895A1 · Dec 2, 2010