Testing method for a semiconductor integrated circuit device, semiconductor integrated circuit device and testing system
A method that divides semiconductor integrated circuit devices (corresponding to S 1 and S 2 ) into a plurality of groups and tests them simultaneously has the semiconductor integrated circuit devices operate with a clock signal (corresponding to CLK 1 and CLK 2 ) having a frequency different from that in other groups in at least one group. A test is performed without decreasing the number of chips tested at one time.
1 . A semiconductor integrated circuit device testing method, comprising:
dividing semiconductor integrated circuit devices into a plurality of groups and tests them simultaneously;
operating said semiconductor integrated circuit devices with a clock signal having a frequency different from that in other groups in at least one group.
2 . The semiconductor integrated circuit device testing method as defined in claim 1 , wherein a testing system generates said clock signal corresponding to each of said groups and supplies said clock signal to said semiconductor integrated circuit devices belonging to each of said groups.
3 . The semiconductor integrated circuit device testing method as defined in claim 1 , wherein said semiconductor integrated circuit devices comprise a frequency division function that divides the frequency of said clock signal supplied; a frequency division ratio of said frequency division function in said at least one group being different from said other groups.
4 . The semiconductor integrated circuit device testing method as defined in claim 1 , wherein said semiconductor integrated circuit devices comprise a frequency division function that divides the frequency of said clock signal supplied and a chip recognition function; in said at least one group, a frequency division ratio of said frequency division function being set differently from said other groups by said chip recognition function.
5 . The semiconductor integrated circuit device testing method as defined claim 1 , wherein the number of said semiconductor integrated circuit devices belonging to each group is about the same.
6 . The semiconductor integrated circuit device testing method as defined in claim 1 , wherein the number of said plurality of groups is two.
7 . The semiconductor integrated circuit device testing method as defined in claim 6 , wherein the frequency of said clock signal in one of said groups and the frequency of said clock signal in another of said groups are alternated at a predetermined interval.
8 . The semiconductor integrated circuit device testing method as defined in claim 1 , wherein a maximum power supply voltage specified for a specification of said semiconductor integrated circuit devices is supplied to said semiconductor integrated circuit devices.
9 . A testing system that performs the testing method as defined in claim 1 .
10 . The testing system as defined in claim 9 comprising:
a burn-in system that generates said clock signal and a burn-in board that mounts said semiconductor integrated circuit devices and supplies said clock signal.
11 . A semiconductor integrated circuit device produced by applying the testing method as defined in claim 1 .
12 . A semiconductor integrated circuit device produced by applying the testing method as defined in claim 4 and arrayed on a wafer.