Granted Patent B2

US 7,923,315 · App. 12/809,876 · Granted Apr 12, 2011

Abstract

Claims (50)

1. A method for fabricating a planar independent-double-gate FET on a bulk semiconductor substrate, the method comprising:

a) providing a substrate with an active semiconductor region laterally defined by an isolation region and with a sacrificial layer buried under a semiconductor layer;

b) depositing a first gate-dielectric layer and a first gate layer, and depositing a hard mask layer on the first gate layer;

c) laterally trimming the first gate-dielectric layer and the first gate layer in a stripe shape so as to cause them to extend, in a channel direction pointing along the longitudinal direction of the FET channels, not only in the active semiconductor region but also on portions of the isolation region;

d) fabricating source and drain regions;

e) fabricating a recess in the isolation region so as to cause the recess to extend, in a depth direction that points towards the inner substrate, to a depth level that provides a lateral access for an etching agent to the buried sacrificial layer and so as to cause the recess to undercut portions of the first gate stack in the channel direction;

f) selectively removing the buried sacrificial layer with the etching agent, thus forming a tunnel with semiconductor tunnel walls in place of the buried sacrificial layer;

g) depositing a second dielectric layer and a second gate layer in the recess and on the semiconductor tunnel walls, thus completing a gate-stack;

h) laterally trimming the gate stack so as to separate top and bottom gate layers.

2. A method for fabricating a planar gate-all-around FET on a bulk semiconductor substrate, the method comprising:

a) providing a substrate with an active semiconductor region laterally defined by an isolation region, with a sacrificial layer buried under a semiconductor layer and with a surface sacrificial layer;

b) depositing a hard mask layer;

c) patterning the hard mask layer in a stripe shape so as to cause the hard mask layer to extend, in a channel direction pointing along the longitudinal direction of the FET channels, not only in the active semiconductor region but also on a part of the isolation region;

d) fabricating source and drain regions;

e) fabricating a recess in the isolation region so as to cause the recess to extend, in a depth direction that points towards the inner substrate, to a depth level that provides a lateral access for an etching agent to the buried sacrificial layer and so as to let the recess undercut portions of the hard mask layer in the channel direction;

f) removing the buried sacrificial layer and the surface sacrificial layer, thus forming tunnels with semiconductor tunnel walls in place of the buried and surface sacrificial layers;

g) depositing a gate stack comprising a dielectric layer and a gate layer in the recess and on the semiconductor tunnel walls, thus completing a gate stack; and

h) trimming the gate stack.

3. The method of claim 1 , wherein the material of the semiconductor substrate and of the semiconductor layer covering the buried sacrificial layer is silicon, and wherein the material of the buried sacrificial layer is silicon-germanium.

4. The method of claim 2 , wherein the material of the semiconductor substrate and of the semiconductor layer covering the buried sacrificial layer is silicon, and wherein the material of the buried sacrificial layer and of the surface sacrificial layer is silicon-germanium.

5. The method of claim 1 , wherein the hard mask layer is made of a dielectric material that is also used for depositing a pre-metal dielectric layer after trimming the gate stack, and wherein the hard mask layer is retained throughout the processing and then embedded into the pre-metal dielectric.

6. The method of claim 1 , wherein trimming the gate stack comprises performing an overetch to separate the top and bottom gate layers.

7. The method of claim 1 , wherein forming a recess in the isolation region comprises exposing the isolation region to an etching agent suitable for an isotropic etching process.

8. The method of claim 2 , wherein forming a recess in the isolation region comprises exposing the isolation region to an etching agent suitable for a predominantly but not fully anisotropic etching process so as to cause a pillar of insulator material of the isolation region to remain at the lateral edges of the hard mask layer at the end of the process of forming the recess, which pillar is used for supporting the hard mask layer after removal of the surface sacrificial layer.

9. The method of claim 1 , wherein a planar bulk FET is concurrently fabricated in a second active semiconductor region by performing the method steps of claim 1 also in the second active semiconductor region, with the exception that

the second active region used for the planar bulk FET is provided without a sacrificial layer;

steps e) and f)of the method of claim 1 are not applied in the second active semiconductor region.

10. The method of claim 2 , wherein the hard mask layer is made of a dielectric material that is also used for depositing a pre-metal dielectric layer after trimming the gate stack, and wherein the hard mask layer is retained throughout the processing and then embedded into the pre-metal dielectric.

11. The method of claim 2 , wherein a planar bulk FET is concurrently fabricated in a second active semiconductor region by performing the method steps of claim 1 also in the second active semiconductor region, with the exception that

the second active region used for the planar bulk FET is provided without a sacrificial layer;

steps e) and f) of the method of claim 1 are not applied in the second active semiconductor region.

12. A method for fabricating a planar independent-double-gate FET and a planar gate-all-around FET on a bulk semiconductor substrate, comprising:

fabricating the planar independent-double gate-FET according to a method, comprising,

1a) providing a substrate-with an active semiconductor region-laterally defined by an isolation region and with a sacrificial layer-buried under a semiconductor layer;

1b) depositing a first gate-dielectric layer-and a first gate layer, and depositing a hard mask layer on the first gate layer;

1c) laterally trimming the first gate-dielectric layer and the first gate layer in a stripe shape so as to cause them to extend, in a channel direction-pointing along the longitudinal direction of the FET channels, not only in the active semiconductor region-but also on portions of the isolation region;

1d) fabricating source and drain regions;

1e) fabricating a recess in the isolation region so as to cause the recess to extend, in a depth direction that points towards the inner substrate, to a depth level that provides a lateral access for an etching agent to the buried sacrificial layer and so as to cause the recess to undercut portions of the first gate stack in the channel direction;

1f) selectively removing the buried sacrificial layer with the etching agent, thus forming a tunnel with semiconductor tunnel walls in place of the buried sacrificial layer;

1g) depositing a second dielectric layer and a second gate layer in the recess and on the semiconductor tunnel walls, thus completing a gate-stack;

1h) laterally trimming the gate stack so as to separate top and bottom gate layers; and

fabricating the planer gate-all-around FET according to a method comprising,

2a) providing a substrate-with an active semiconductor region -laterally defined by an isolation region, with a sacrificial layer buried under a semiconductor layer and with a surface sacrificial layer;

2b) depositing a hard mask layer;

2c) patterning the hard mask layer in a stripe shape so as to cause the hard mask layer to extend, in a channel direction pointing along the longitudinal direction of the FET channels, not only in the active semiconductor region but also on a part of the isolation region;

2d) fabricating source and drain regions;

2e) fabricating a recess in the isolation region so as to cause the recess to extend, in a depth direction that points towards the inner substrate, to a depth level that provides a lateral access for an etching agent to the buried sacrificial layer and so as to let the recess undercut portions of the hard mask layer in the channel direction;

2f) removing the buried sacrificial layer-and the surface sacrificial layer, thus forming tunnels with semiconductor tunnel walls in place of the buried and surface sacrificial layers;

2g) depositing a gate stack comprising a dielectric layer and a gate layer in the recess and on the semiconductor tunnel walls, thus completing a gate stack; and

2h) trimming the gate stack.

Assignments (13)