IP Library Granted Patent US 8,389,330
Granted Patent B2
US 8,389,330 · App. 12/822,659 · Granted Mar 5, 2013

Integrated circuit package system with package stand-off and method of manufacture thereof

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Quick Facts
Patent No.
US 8,389,330
App. No.
12/822,659
Granted
Mar 5, 2013
Kind
B2
Abstract

A method of manufacture of an integrated circuit package system includes: providing a penetrable layer; partially immersing leads in the penetrable layer; coupling an integrated circuit die to the leads; molding a package body on the integrated circuit die, the leads, and the penetrable layer; and exposing stand-off leads from the leads by removing the penetrable layer including establishing a stand-off height between a bottom of the package body and the bottom of the stand-off leads.

Claims (55)

1. A method of manufacture of an integrated circuit package system comprising:

providing a penetrable layer;

partially immersing leads in the penetrable layer;

coupling an integrated circuit die to the leads;

molding a package body on the integrated circuit die, the leads, and the penetrable layer; and

exposing stand-off leads from the leads by removing the penetrable layer including establishing a stand-off height between a bottom of the package body and the bottom of the stand-off leads and the bottom of the package body having a meniscus protrusion extending out of the package body with the meniscus protrusion directly on the stand-off leads.

2. The method as claimed in claim 1 further comprising exposing a stand-off die attach pad surrounded by the leads for supporting the integrated circuit die.

3. The method as claimed in claim 1 further comprising:

positioning a flip chip die, having system interconnects immersed in the penetrable layer, among the leads; and

coupling electrical interconnects between the integrated circuit die and the leads.

4. The method as claimed in claim 1 further comprising positioning a ball grid array package among the leads including immersing system interconnects in the penetrable layer.

5. The method as claimed in claim 1 further comprising:

positioning an inverted internal stacking module among the leads including immersing a stacking package body in the penetrable layer;

connecting a coupling pad, on the internal stacking module, to the leads; and

exposing the stacking package body in the stand-off height.

6. A method of manufacture of an integrated circuit package system comprising:

fabricating a lead frame having leads including forming leads or stacking leads;

providing a penetrable layer having a precisely measured thickness;

partially immersing the lead frame including the leads or the stacking leads in the penetrable layer;

coupling an integrated circuit die to the leads or the stacking leads;

molding a package body on the integrated circuit die, the lead frame, and the penetrable layer including forming a bottom of the package body by the penetrable layer;

exposing stand-off leads or stacking stand-off leads from the lead frame by removing the penetrable layer from the leads or stacking leads and the bottom of the package body having a meniscus protrusion extending out of the package body with the meniscus protrusion directly on the stand-off leads; and

singulating a stand-off package having the stand-off leads or the stacking stand-off leads including a establishing a stand-off height between the bottom of the package body and the bottom of the stand-off leads or stacking stand-off leads.

7. The method as claimed in claim 6 further comprising exposing a stand-off die attach pad in the lead frame for supporting the integrated circuit die including applying an adhesive between the stand-off die attach pad and the integrated circuit die.

8. The method as claimed in claim 6 further comprising:

positioning a flip chip die, having system interconnects immersed in the penetrable layer, between the leads wherein positioning the flip chip die includes positioning a through silicon via die having an integrated circuit; and

coupling electrical interconnects between the integrated circuit die and the leads including coupling the system interconnects between the through silicon via die and the integrated circuit die.

9. The method as claimed in claim 6 further comprising positioning a ball grid array package between the leads including immersing system interconnects in the penetrable layer by partially or fully immersing the system interconnects for establishing the stand-off height.

10. The method as claimed in claim 6 further comprising:

positioning an inverted internal stacking module between the leads including positioning a substrate, of the internal stacking module, under the integrated circuit die and immersing a stacking package body in the penetrable layer;

connecting a coupling pad, on the internal stacking module, to the leads including the integrated circuit die coupled to the stand-off leads through the substrate; and

exposing the stacking package body in the stand-off height.

11. An integrated circuit package system comprising:

stand-off leads positioned along an edge;

an integrated circuit die coupled to the stand-off leads; and

a package body molded on the integrated circuit die and the stand-off leads includes a bottom of the package body formed a stand-off height above the bottom of the stand-off leads and the bottom of the package body having a meniscus protrusion extending out of the package body with the meniscus protrusion directly on the stand-off leads.

12. The system as claimed in claim 11 further comprising a stand-off die attach pad positioned between the stand-off leads for supporting the integrated circuit die.

13. The system as claimed in claim 11 further comprising:

a flip chip die, having system interconnects to protrude from the bottom, between the stand-off leads; and

electrical interconnects coupled between the integrated circuit die and the stand-off leads.

14. The system as claimed in claim 11 further comprising a ball grid array package between the stand-off leads includes system interconnects to protrude from the bottom of the package body.

15. The system as claimed in claim 11 further comprising:

an inverted internal stacking module between the stand-off leads;

a coupling pad, on the internal stacking module, coupled to the stand-off leads; and

a stacking package body, to protrude from the bottom of the package body, exposed in the stand-off height.

16. The system as claimed in claim 11 wherein stand-off leads positioned includes stacking stand-off leads.

17. The system as claimed in claim 16 further comprising a stand-off die attach pad positioned between the stand-off leads for supporting the integrated circuit die includes an adhesive between the integrated circuit die and the stand-off die attach pad.

18. The system as claimed in claim 16 further comprising:

a flip chip die, having system interconnects to protrude from the bottom, between the stand-off leads wherein the flip chip die includes a through silicon via die having an integrated circuit; and

electrical interconnects coupled between the integrated circuit die and the stand-off leads includes the system interconnects coupled from the through silicon via die to the integrated circuit die.

19. The system as claimed in claim 16 further comprising a ball grid array package between the stand-off leads includes system interconnects to protrude from the bottom of the package body including the system interconnects partially or fully protrude for establishing the stand-off height.

20. The system as claimed in claim 16 further comprising:

an inverted internal stacking module between the stand-off leads includes a substrate, of the internal stacking module, under the integrated circuit die;

a coupling pad, on the internal stacking module, coupled to the stand-off leads includes the integrated circuit die coupled to the stand-off leads through the substrate; and

a stacking package body, to protrude from the bottom of the package body, exposed in the stand-off height.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME ON THE COVER SHEET FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. PREVIOUSLY RECORDED ON REEL 038378 FRAME 0244. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065239/0786 →
RELEASE OF SECURITY INTEREST Recorded Jun 5, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052850/0237 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0244 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2010
From: DO, BYUNG TAI; CHUA, LINDA PEI EE; PAGAILA, REZA ARGENTY
To: STATS CHIPPAC LTD.
Reel/Frame 024625/0649 →