Electronic device including a gate electrode having portions with different conductivity types
View Patent ↗An electronic device can include a gate electrode having different portions with different conductivity types. In an embodiment, a process of forming the electronic device can include forming a semiconductor layer over a substrate, wherein the semiconductor layer has a particular conductivity type. The process can also include selectively doping a region of the semiconductor layer to form a first doped region having an opposite conductivity type. The process can further include patterning the semiconductor layer to form a gate electrode that includes a first portion and a second portion, wherein the first portion includes a portion of the first doped region, and the second region includes a portion of the semiconductor layer outside of the first doped region. In a particular embodiment, the electronic device can have a gate electrode having edge portions of one conductivity type and a central portion having an opposite conductivity type.
1. An electronic device comprising:
a first source/drain region;
a second source/drain region spaced apart from the first source/drain region;
a channel region disposed between the first and second source drain regions; and
a gate electrode having a first edge portion, a second edge portion, and a central portion disposed between and abutting the first and second edge portions, wherein:
the central portion has a first conductivity type, and the first and second edge portions have a second conductivity type opposite the first conductivity type;
the central portion is disposed over the channel region, wherein the central portion is narrower at a first elevation closer to the channel region than at a second elevation further from the channel region;
the first edge portion at least partly overlaps the first source/drain region, wherein the first edge portion is wider at the first elevation than at the second elevation; and
the second edge portion at least partly overlaps the second source/drain region.
2. The electronic device of claim 1 , wherein a boundary between the central portion and the first edge portion is in a shape of an arc.
3. The electronic device of claim 2 , wherein the first edge portion has an uppermost flattened surface.
4. The electronic device of claim 1 , wherein the first edge portion has an uppermost flattened surface.
5. The electronic device of claim 1 , wherein the second edge portion is wider at the first elevation than at the second elevation.
6. The electronic device of claim 5 , wherein boundaries between the central portion and the first edge portion and between the central portion and the second edge portion are in shapes of arcs.
7. The electronic device of claim 5 , wherein:
the first and second edge portions have flattened uppermost surfaces; and
an uppermost surface of the central portion and the flattened uppermost surfaces lie along a same plane.
8. The electronic device of claim 7 , further comprising a conductive member that directly contacts the flattened uppermost surfaces of the first and second edge portions and the uppermost surface of the central portion.
9. The electronic device of claim 1 , wherein the central portion, the first edge portion, and the second edge portion are different portions of a same semiconductor layer.
10. The electronic device of claim 1 , further comprising a substrate having a primary surface, wherein each the first and second edge portions have a surface opposite the central portion, wherein the surface is substantially perpendicular to the primary surface.
11. The electronic device of claim 1 , further comprising a gate dielectric layer disposed between the channel region and the gate electrode, wherein along a surface of the gate electrode closest to the gate dielectric layer:
the central portion of the gate electrode overlaps substantially none of the first and second source/drain region;
the first edge portion of the gate electrode at least partly overlaps the channel region; and
the second edge portion of the gate electrode at least partly overlaps the channel region.
12. The electronic device of claim 11 , wherein the channel region has the first conductivity type, and the first and second source/drain regions have the second conductivity type.
13. The electronic device of claim 12 , further comprising a charge storage layer, wherein the charge storage layer is disposed between the gate dielectric layer and the gate electrode.
14. The electronic device of claim 13 , wherein the charge storage layer comprises a nitride layer.
15. The electronic device of claim 1 , wherein from a cross-sectional view, the gate electrode is substantially rectangular.
16. The electronic device of claim 1 , further comprising a substrate having a primary surface, wherein from a cross-sectional view, a first surface of the gate electrode closest to the primary surface is significantly longer than a second surface of the gate electrode farthest from the primary surface.
17. The electronic device of claim 1 , wherein the second edge portion is wider at the first elevation than at the second elevation.
18. An electronic device comprising:
a first source/drain region and a first pocket region, the first pocket region abutting the first source/drain region and a channel region, the first source/drain region having a first conductivity type, the first pocket region and the channel region having a second conductivity type opposite the first conductivity type;
a second source/drain region spaced apart from the first source/drain region and a second pocket region, the second pocket region abutting the second source/drain region and the channel region, the second pocket region having the second conductivity type, and thea channel region disposed between the first and second source drain regions; and
a gate electrode having a first edge portion, a second edge portion, and a central portion disposed between and abutting the first and second edge portions, wherein:
the central portion and the first and second pocket regions have a first conductivity type, and the first and second edge portions have a second conductivity type opposite the first conductivity type;
the central portion is disposed over the channel region;
the first edge portion at least partly overlaps the first source/drain region; and
the second edge portion at least partly overlaps the second source/drain region.