Granted Patent B2

US 8,728,859 · App. 12/855,079 · Granted May 20, 2014

Abstract

Claims (22)

1. A method for fabricating a phase change memory cell, the method comprising:

forming a non-sublithographic via within an insulating substrate, the insulating substrate embedded in the same layer as a first metalization layer (Metal 1) of a multi-level metal interconnect of a semiconductor wafer, the non-sublithographic via including a bottom and a sidewall;

forming a sublithographic aperture through the bottom of the non-sublithographic via, the sublithographic aperture extending to a buried conductive material;

filling the sublithographic aperture with a conductive non-phase change material; and

depositing a phase change material within the non-sublithographic via.

2. The method of clam 1 , further forming an overhang above the non-sublithographic via.

3. The method of claim 2 , wherein forming the overhang includes performing a buffered oxide etch such that the sidewall of the non-sublithographic via is selective etched.

4. The method of claim 1 , further comprising forming a sublithographic mask within the non-sublithographic via.

5. The method of claim 4 , wherein forming the sublithographic mask comprises:

filling the non-sublithographic via with a conformal material to form a keyhole cavity within the non-sublithographic via;

etching through the conformal material such that a step spacer is formed by the conformal material within the non-sublithographic via.

6. The method of claim 5 , wherein forming the sublithographic aperture includes selectively etching an intermediate insulating layer below the step spacer.

7. The method of claim 1 , wherein filling the sublithographic aperture with the conductive non-phase change material includes performing a chemical vapor deposition of the conductive non-phase change material within the sublithographic aperture.

8. The method of claim 1 , further comprising electrically isolating the conductive non-phase change material along the sidewall of the non-sublithographic via from the conductive non-phase change material filled in the sublithographic aperture.

9. The method of claim 8 , wherein electrically isolating the conductive non-phase change material includes performing a reactive ion etch to remove the conductive non-phase change material from the bottom of the non-sublithographic via.

10. The method of claim 1 , wherein depositing the phase change material within the non-sublithographic via includes performing a physical vapor deposition of the phase change material within the non-sublithographic via.

11. The method of claim 1 , further comprising recessing the phase change material within the non-sublithographic via.

12. The method of claim 11 , wherein recessing the phase change material within the non-sublithographic via includes performing a chemical mechanical polish on the phase change material.

13. The method of claim 1 , further depositing a top electrode over the phase change material within the non-sublithographic via.

14. The method of claim 13 , further comprising recessing the top electrode above the non-sublithographic via.

15. The method of claim 14 , wherein recessing the top electrode above the non-sublithographic via includes performing a chemical mechanical polish on the top conductive material.

16. The method of claim 15 , further comprising depositing a CMP stop layer above the insulating substrate, the CMP stop layer configured to inhibit the chemical mechanical polish of the insulating substrate.

Assignments (6)