IP Library Granted Patent US 8,212,288
Granted Patent B2
US 8,212,288 · App. 12/879,035 · Granted Jul 3, 2012

Compound semiconductor substrate comprising a multilayer buffer layer

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Quick Facts
Patent No.
US 8,212,288
App. No.
12/879,035
Granted
Jul 3, 2012
Kind
B2
Abstract

A compound semiconductor substrate which inhibits the generation of a crack or a warp and is preferable for a normally-off type high breakdown voltage device, arranged that a multilayer buffer layer 2 in which Al x Ga 1-x N single crystal layers (0.6≦X≦1.0) 21 containing carbon from 1×10 18 atoms/cm 3 to 1×10 21 atoms/cm 3 and Al y Ga 1-y N single crystal layers (0.1≦y≦0.5) 22 containing carbon from 1×10 17 atoms/cm 3 to 1×10 21 atoms/cm 3 are alternately and repeatedly stacked in order, and a nitride active layer 3 provided with an electron transport layer 31 having a carbon concentration of 5×10 17 atoms/cm 3 or less and an electron supply layer 32 are deposited on a Si single crystal substrate 1 in order. The carbon concentrations of the Al x Ga 1-x N single crystal layers 21 and that of the AlGa 1-y N single crystal layers 22 respectively decrease from the substrate 1 side towards the above-mentioned active layer 3 side. In this way, the compound semiconductor substrate is produced.

Claims (33)

1. A compound semiconductor substrate, arranged such that a multilayer buffer layer in which Al x Ga 1-x N single crystal layers (0.6≦X≦1.0) containing carbon from 1×10 18 atoms/cm 3 to 1×10 21 atoms/cm 3 and Al y Ga 1-y N single crystal layers (0≦y≦0.5) containing carbon from 1×10 17 atoms/cm 3 to 1×10 21 atoms/cm 3 are alternately and repeatedly stacked, and a nitride active layer comprising an electron transport layer having a carbon concentration of 5×10 17 atoms/cm 3 or less and an electron supply layer are deposited successively on a Si single crystal substrate, wherein

a carbon concentration of said Al x Ga 1-x N single crystal layers and a carbon concentration of said Al y Ga 1-y N single crystal layers respectively decreases from said Si single crystal substrate side towards said active layer side.

2. The compound semiconductor substrate as claimed in claim 1 , wherein said Al y Ga 1-y N single crystal layers are of 0.1≦y≦0.5.

3. The compound semiconductor substrate as claimed in claim 1 , wherein the carbon concentration of one of said Al x Ga 1-x N single crystal layers is higher than the carbon concentration of one of said Al y Ga 1-y N single crystal layers immediately above the former.

4. The compound semiconductor substrate as claimed in claim 2 , wherein the carbon concentration of one of said Al x Ga 1-x N single crystal layers is higher than the carbon concentration of one of said Al y Ga 1-y N single crystal layers immediately above the former.

5. The compound semiconductor substrate as claimed in claim 1 , wherein said multilayer buffer layer contains boron from 5×10 16 atoms/cm 3 to 1×10 19 atoms/cm 3 .

6. The compound semiconductor substrate as claimed in claim 2 , wherein said multilayer buffer layer contains boron from 5×10 16 atoms/cm 3 to 1×10 19 atoms/cm 3 .

7. The compound semiconductor substrate as claimed in claim 3 , wherein said multilayer buffer layer contains boron from 5×10 16 atoms/cm 3 to 1×10 19 atoms/cm 3 .

8. The compound semiconductor substrate as claimed in claim 4 , wherein said multilayer buffer layer contains boron from 5×10 16 atoms/cm 3 to 1×10 19 atoms/cm 3.

9. The compound semiconductor substrate as claimed in claim 1 , wherein said electron transport layer is an Al z Ga 1-z N single crystal layer (0≦z≦0.01).

10. The compound semiconductor substrate as claimed in claim 2 , wherein said electron transport layer is an Al z Ga 1-z N single crystal layer (0≦z≦0.01).

11. The compound semiconductor substrate as claimed in claim 3 , wherein said electron transport layer is an Al z Ga 1-z N single crystal layer (0≦z≦0.01).

12. The compound semiconductor substrate as claimed in claim 4 , wherein said electron transport layer is an Al z Ga 1-z N single crystal layer (0≦z≦0.01).

13. The compound semiconductor substrate as claimed in claim 5 , wherein said electron transport layer is an Al z Ga 1-z N single crystal layer (0≦z≦0.01).

14. The compound semiconductor substrate as claimed in claim 6 , wherein said electron transport layer is an Al z Ga 1-z N single crystal layer (0≦z≦0.01).

15. The compound semiconductor substrate as claimed in claim 7 , wherein said electron transport layer is an Al z Ga 1-z N single crystal layer (0≦z≦0.01).

16. The compound semiconductor substrate as claimed in claim 8 , wherein said electron transport layer is an Al z Ga 1-z N single crystal layer (0≦z≦0.01).

17. The compound semiconductor substrate as claimed in claim 1 , wherein said electron transport layer has a thickness of from 1 nm to 500 nm and said compound semiconductor substrate is used for a normally-off type switching device.

18. The compound semiconductor substrate as claimed in claim 2 , wherein said electron transport layer has a thickness of from 1 nm to 500 nm and said compound semiconductor substrate is used for a normally-off type switching device.

19. The compound semiconductor substrate as claimed in claim 3 , wherein said electron transport layer has a thickness of from 1 nm to 500 nm and said compound semiconductor substrate is used for a normally-off type switching device.

20. The compound semiconductor substrate as claimed in claim 4 , wherein said electron transport layer has a thickness of from 1 nm to 500 nm and said compound semiconductor substrate is used for a normally-off type switching device.

21. The compound semiconductor substrate as claimed in claim 5 , wherein said electron transport layer has a thickness of from 1 nm to 500 nm and said compound semiconductor substrate is used for a normally-off type switching device.

22. The compound semiconductor substrate as claimed in claim 6 , wherein said electron transport layer has a thickness of from 1 nm to 500 nm and said compound semiconductor substrate is used for a normally-off type switching device.

23. The compound semiconductor substrate as claimed in claim 7 , wherein said electron transport layer has a thickness of from 1 nm to 500 nm and said compound semiconductor substrate is used for a normally-off type switching device.

24. The compound semiconductor substrate as claimed in claim 8 , wherein said electron transport layer has a thickness of from 1 nm to 500 nm and said compound semiconductor substrate is used for a normally-off type switching device.

25. The compound semiconductor substrate as claimed in claim 9 , wherein said electron transport layer has a thickness of from 1 nm to 500 nm and said compound semiconductor substrate is used for a normally-off type switching device.

26. The compound semiconductor substrate as claimed in claim 10 , wherein said electron transport layer has a thickness of from 1 nm to 500 nm and said compound semiconductor substrate is used for a normally-off type switching device.

27. The compound semiconductor substrate as claimed in claim 11 , wherein said electron transport layer has a thickness of from 1 nm to 500 nm and said compound semiconductor substrate is used for a normally-off type switching device.

28. The compound semiconductor substrate as claimed in claim 12 , wherein said electron transport layer has a thickness of from 1 nm to 500 nm and said compound semiconductor substrate is used for a normally-off type switching device.

29. The compound semiconductor substrate as claimed in claim 13 , wherein said electron transport layer has a thickness of from 1 nm to 500 nm and said compound semiconductor substrate is used for a normally-off type switching device.

30. The compound semiconductor substrate as claimed in claim 14 , wherein said electron transport layer has a thickness of from 1 nm to 500 nm and said compound semiconductor substrate is used for a normally-off type switching device.

31. The compound semiconductor substrate as claimed in claim 15 , wherein said electron transport layer has a thickness of from 1 nm to 500 nm and said compound semiconductor substrate is used for a normally-off type switching device.

32. The compound semiconductor substrate as claimed in claim 16 , wherein said electron transport layer has a thickness of from 1 nm to 500 nm and said compound semiconductor substrate is used for a normally-off type switching device.

Assignments (3)
CHANGE OF NAME Recorded May 2, 2024
From: COORSTEK KK
To: COORSTEK GK
Reel/Frame 067565/0354 →
CHANGE OF NAME & ADDRESS Recorded Apr 11, 2016
From: COVALENT MATERIALS CORPORATION
To: COORSTEK KK
Reel/Frame 038399/0880 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 10, 2010
From: KOMIYAMA, JUN; ERIGUCHI, KENICHI; OISHI, HIROSHI; ABE, YOSHIHISA; YOSHIDA, AKIRA; SUZUKI, SHUNICHI
To: COVALENT MATERIALS CORPORATION
Reel/Frame 024966/0259 →