IP Library Granted Patent US 8,163,577
Granted Patent B2
US 8,163,577 · App. 12/879,692 · Granted Apr 24, 2012

Methods of forming light emitting devices having current reducing structures

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Quick Facts
Patent No.
US 8,163,577
App. No.
12/879,692
Granted
Apr 24, 2012
Kind
B2
Abstract

A light emitting device includes a p-type semiconductor layer, an n-type semiconductor layer, and an active region between the n-type semiconductor layer and the p-type semiconductor layer. A non-transparent feature, such as a wire bond pad, is on the p-type semiconductor layer or on the n-type semiconductor layer opposite the p-type semiconductor layer, and a reduced conductivity region is in the p-type semiconductor layer or the n-type semiconductor layer and is aligned with the non-transparent feature. The reduced conductivity region may extend from a surface of the p-type semiconductor layer opposite the n-type semiconductor layer towards the active region and/or from a surface of the n-type semiconductor layer opposite the p-type semiconductor layer towards the active region.

Claims (26)

1. A method of forming a light emitting device, comprising:

forming a p-type semiconductor layer, an n-type semiconductor layer, and an active region between the n-type semiconductor layer and the p-type semiconductor layer;

forming a non-transparent feature on the n-type semiconductor layer opposite the p-type semiconductor layer; and

forming a reduced conductivity region in the p-type semiconductor layer, wherein edges of the reduced conductivity region are aligned with edges of the non-transparent feature, the reduced conductivity region extending from a surface of the p-type semiconductor layer opposite the n-type semiconductor layer towards the active region.

2. The method of claim 1 , wherein forming a non-transparent feature on the n-type semiconductor layer comprises forming a wire bond pad, a current spreading finger and/or a passivation region on the n-type semiconductor layer.

3. The method of claim 1 , wherein the reduced conductivity region extends from the surface of the p-type semiconductor layer to the active region.

4. The method of claim 1 , wherein the reduced conductivity region extends from the surface of the p-type semiconductor layer into the active region.

5. The method of claim 1 , wherein the reduced conductivity region extends from the surface of the p-type semiconductor layer through the active region.

6. The method of claim 1 , wherein the reduced conductivity region extends through the active region.

7. The method of claim 1 , wherein the active region comprises a Group III-nitride based active region.

8. The method of claim 1 , wherein forming a reduced conductivity region comprises:

forming a mask layer on the surface of the p-type semiconductor layer, the mask layer having an opening corresponding to the bond pad region; and

implanting atoms into the p-type semiconductor layer through the opening in the mask layer.

9. A method of forming a light emitting device, comprising:

forming a p-type semiconductor layer, an n-type semiconductor layer, and an active region between the n-type semiconductor layer and the p-type semiconductor layer;

forming a wire bond pad on the n-type semiconductor layer opposite the p-type semiconductor layer; and

forming a metal contact on a surface of the p-type semiconductor layer opposite the n-type semiconductor layer, wherein the metal contact forms an ohmic contact to the p-type semiconductor layer in a region other than a reduced conductivity area of the surface of the p-type semiconductor layer, wherein edges of the reduced conductivity area are aligned with edges of the wire bond pad.

10. The method of claim 9 , further comprising forming a reduced conductivity region in the p-type semiconductor layer and aligned with the wire bond pad and the reduced conductivity area, the reduced conductivity region extending from the surface of the p-type semiconductor layer towards the active region.

11. The method of claim 9 , further comprising forming a reduced conductivity region in the n-type semiconductor layer and aligned with the wire bond pad, the reduced conductivity region extending from a surface of the n-type semiconductor layer opposite the p-type semiconductor layer towards the active region.

12. The method of claim 9 , further comprising forming a non-ohmic contact on the surface of the p-type semiconductor layer.

13. The method of claim 12 , wherein the non-ohmic contact comprises a metal that does not form an ohmic contact with the p-type semiconductor layer.

14. A method of forming a light emitting device, comprising:

forming a p-type semiconductor layer, an n-type semiconductor layer, and an active region between the n-type semiconductor layer and the p-type semiconductor layer;

forming a wire bond pad on the n-type semiconductor layer opposite the p-type semiconductor layer;

forming a metal contact on a surface of the p-type semiconductor layer opposite the n-type semiconductor layer, wherein the metal contact forms on ohmic contact to the p-type semiconductor layer in a region other than a reduced conductivity area of the surface of the p-type semiconductor layer that is aligned with the wire bond pad; and

forming a reduced conductivity region in the n-type semiconductor layer and aligned with the wire bond pad, the reduced conductivity region extending from a surface of the n-type semiconductor layer opposite the p-type semiconductor layer towards the active region, wherein the non-ohmic contact comprises an insulator on the surface of the p-type semiconductor layer.

Assignments (5)
PATENT SECURITY AGREEMENT Recorded Jun 30, 2025
From: CREELED, INC.; PENGUIN SOLUTIONS CORPORATION (DE); SMART EMBEDDED COMPUTING, INC.; SMART HIGH RELIABILITY SOLUTIONS LLC; SMART MODULAR TECHNOLOGIES, INC.; PENGUIN COMPUTING, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 071755/0001 →
RELEASE OF PATENT SECURITY INTEREST RECORDED AT R/F 058983/0001 Recorded Jun 25, 2025
From: CITIZENS BANK, N.A.
To: SMART MODULAR TECHNOLOGIES, INC.; SMART EMBEDDED COMPUTING, INC.; SMART HIGH RELIABILITY SOLUTIONS LLC; CREELED, INC.
Reel/Frame 071725/0207 →
SECURITY INTEREST Recorded Feb 7, 2022
From: SMART MODULAR TECHNOLOGIES, INC.; SMART HIGH RELIABILITY SOLUTIONS, LLC; SMART EMBEDDED COMPUTING, INC.; CREELED, INC.
To: CITIZENS BANK, N.A.
Reel/Frame 058983/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2021
From: CREE, INC.
To: CREELED, INC.
Reel/Frame 055911/0577 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2017
From: EMERSON, DAVID TODD; HABERERN, KEVIN; BERGMANN, MICHAEL JOHN; SLATER, DAVID B., JR.; DONOFRIO, MATTHEW; EDMOND, JOHN
To: CREE, INC.
Reel/Frame 041333/0788 →