Chip scale module package in BGA semiconductor package
A semiconductor package includes a ball grid array (BGA) substrate having integrated metal layer circuitry, a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD), the flip chip chip scale module package attached to the BGA substrate, and an application die attached to the IPD. A method of manufacturing a semiconductor package includes providing a BGA substrate having integrated metal layer circuitry, attaching a flip chip CSMP having a first IPD to the BGA substrate, and attaching an application die to the IPD.
1. A semiconductor device, comprising:
a ball grid array (BGA) substrate including integrated metal layers;
a plurality of first interconnects connected to the integrated metal layers of the BGA substrate;
a known good chip scale module package (CSMP) electrically coupled to the first interconnects, wherein the CSMP includes:
(a) a second substrate including a cutout area,
(b) a plurality of second interconnects electrically coupled to a first surface of the second substrate,
(c) a first semiconductor die mounted over the second substrate and electrically coupled to the plurality of second interconnects,
(d) a plurality of third interconnects electrically coupled to a first surface of the first semiconductor die,
(e) a second semiconductor die disposed in the cutout area of the second substrate and electrically coupled to the third interconnects, wherein a surface of the second semiconductor die opposite the third interconnects contacts the BGA substrate for thermal dissipation, and
(f) an underfill material deposited between the first semiconductor die and second semiconductor die;
a third semiconductor die mounted over the CSMP;
a plurality of fourth interconnects electrically coupled between the third semiconductor die and the second substrate; and
a plurality of fifth interconnects electrically coupled between the third semiconductor die and the BGA substrate.
2. The semiconductor device of claim 1 , wherein the plurality of first interconnects comprises an adhesive material, including solder paste, solder flux, or conductive epoxy.
3. The semiconductor device of claim 1 , further including an encapsulant deposited over the fourth and fifth interconnects, the third semiconductor die, the CSMP, and the BGA substrate.
4. The semiconductor device of claim 1 , wherein the plurality of fourth and fifth interconnects includes wire bonds.
5. The semiconductor device of claim 1 , wherein the CSMP is disposed in a cavity of the BGA substrate.
6. A semiconductor device, comprising:
a first substrate including integrated metal layers;
a known good chip scale module package (CSMP) electrically coupled to the first substrate;
a first semiconductor die disposed over the CSMP;
a first bond wire extending from the first semiconductor die to the first substrate;
a second bond wire extending from the first semiconductor die to the CSMP;
a second substrate including a cutout area;
a second semiconductor die disposed over the second substrate; and
a third semiconductor die disposed in the cutout area of the second substrate and mounted to the second semiconductor die.
7. The semiconductor device of claim 6 , further including an underfill material disposed between the second semiconductor die and third semiconductor die.
8. The semiconductor device of claim 6 , further including a plurality of first interconnects electrically connecting the first substrate to the CSMP.
9. The semiconductor device of claim 6 , further including an encapsulant deposited over the first semiconductor die, the CSMP, and the first substrate.
10. The semiconductor device of claim 6 , wherein the CSMP is disposed in a cavity of the first substrate.
11. The semiconductor device of claim 6 , wherein a surface of the third semiconductor die contacts the first substrate for thermal dissipation.
12. A semiconductor device, comprising:
a first substrate;
a plurality of first interconnects electrically coupled to the first substrate;
a second substrate including a cutout area completely through the second substrate, the second substrate electrically coupled to the first interconnects;
a first semiconductor die disposed over the second substrate;
a plurality of second interconnects electrically coupled to the second substrate and first semiconductor die;
a second semiconductor die disposed in the cutout area of the second substrate;
a plurality of third interconnects electrically coupled to the second semiconductor die and first semiconductor die;
a third semiconductor die disposed over the first semiconductor die;
a first bond wire formed between the third semiconductor die and the first substrate; and
a second bond wire formed between the third semiconductor die and the second substrate.
13. The semiconductor device of claim 12 , wherein a surface of the third semiconductor die contacts the first substrate for thermal dissipation.
14. The semiconductor device of claim 12 , further including a plurality of bumps formed over the first substrate.
15. The semiconductor device of claim 12 , further including an encapsulant deposited over the first semiconductor die, third semiconductor die, first substrate, second substrate, first bond wire, and second bond wire.