STRUCTURE AND METHOD FOR SEMICONDUCTOR TESTING
An embodiment of a test structure in accordance with the present invention comprises a pair of interdigitated comb portions of a metallization layer present in a recess of an inter-layer dielectric (ILD) formed over a polysilicon heater element. A third portion of the metallization layer comprises a serpentine metal line interposed between the comb portions. Application of force voltages, and detection of sense voltages, at various nodes of the metallization portions allows identification of the following: (1) electromigration of metal in the metallization portions; (2) extrusion of metal from one metallization portion to contact another; (3) breakdown voltage (V bd ) and time dependent dielectric breakdown (TDDB) of the ILD; (4) contamination in the metallization portions with mobile ions; and (5) k valve and drift in k value of the ILD. A bias voltage may be applied to the polysilicon heater to accomplish temperature control during testing.
1 . A test structure comprising:
a polysilicon pad formed on a substrate;
a dielectric layer formed on the polysilicon pad; and
a metallization layer formed in a recess in the dielectric layer, the metallization layer comprising a first comb portion interdigitated with and electrically isolated from a second comb portion by the dielectric layer.
2 . The test structure of claim 1 further comprising a first force node positioned at a first end of the first comb portion, a second force node positioned at a first end of the second comb portion, and a sense node positioned at an opposite end of the second comb portion.
3 . The test structure of claim 1 , wherein the metallization layer further comprises a serpentine portion positioned between the first comb portion and the second comb portion.
4 . The test structure of claim 3 wherein the serpentine portion comprises a first sense node and a first force node positioned at a first end, and a second sense node and a second force node positioned at an opposite end.
5 . The test structure of claim 1 , wherein the metallization layer comprises copper.
6 . The test structure of claim 1 , wherein the metallization layer comprises aluminum.
7 . A method of testing a semiconductor substrate comprising:
providing a test structure comprising a polysilicon pad formed on a substrate, a dielectric layer formed on the polysilicon pad, and a metallization layer formed in a recess in the dielectric layer, the metallization layer comprising a first comb portion interdigitated with a second comb portion and electrically isolated from the second comb portion by the dielectric layer; and
applying a force voltage at a force node of the first comb portion.
8 . The method of claim 7 further comprising detecting a change in a sense voltage over time at a first end of the first comb portion opposite to a second end of the first comb portion to which the voltage was applied, the changed sense voltage indicating a change in resistance of the first comb portion attributable to electromigration of metal in the first comb portion.
9 . The method of claim 7 , wherein the voltage is maintained constant over time.
10 . The method of claim 7 further comprising detecting a sense voltage at an end of the second comb portion, the sense voltage indicating extrusion of metal from the first comb portion.
11 . The method of claim 7 further comprising applying a bias voltage to the polysilicon pad to increase a temperature of the first comb portion, and detecting a change in sense voltage over time in the first comb portion, the changed sense voltage indicating a breakdown of the dielectric layer.
12 . The method of claim 11 , wherein the bias voltage is increased over time.
13 . The method of claim 7 , wherein the force voltage is maintained constant over time.
14 . The method of claim 7 further comprising applying a bias voltage to the polysilicon pad to increase a temperature of the first comb portion, and wherein the force voltage comprises a triangular voltage sweep to detect mobile ions in the first comb portion.
15 . The method of claim 7 further comprising sensing a voltage in the second comb portion to indicate a dielectric k value for the dielectric layer.
16 . The method of claim 15 , wherein a change in the sense voltage over time indicates a drift in the dielectric layer k value.
17 . The method of claim 7 further comprising applying a bias voltage to the polysilicon pad to heat the dielectric layer.
18 . The method of claim 7 , wherein interdigitated portions of the first and second comb portions are substantially parallel to one another, such that an absolute k value of the dielectric layer may be determined based upon a known distance between the interdigitated comb portions, a known area of the interdigitated comb portions, and a capacitance between the first and second comb portions calculated from the sense voltage.
19 . The method of claim 7 further comprising a serpentine metal line interposed between the first and second comb portions, the serpentine having a sense node at each end.
20 . The method of claim 19 , wherein the detection of a sense voltage at the sense node of the serpentine metal line indicates a bridge between the serpentine and the first comb portion or the second comb portion when the voltage is applied to the first or second comb portion.