IP Library Granted Patent US 8,653,864
Granted Patent B2
US 8,653,864 · App. 12/893,755 · Granted Feb 18, 2014

Reset circuit

Inventor: Susumu Yamada (Oizumi-machi, JP)
Assignee: Semiconductor Components Industries, LLC
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,653,864
App. No.
12/893,755
Granted
Feb 18, 2014
Kind
B2
Abstract

In some embodiments, a reset circuit for an electronic circuit equipped with a backup power capacitor includes a first detector arranged to detect a predetermined first voltage of the backup capacitor, a second detector arranged to detect a predetermined second voltage of the backup capacitor, the second voltage being lower than the first voltage, and a controller arranged to control an output of a reset request signal based on detection results of the first detector and the second detector. The controller is configured to output the reset request signal when the first detector detects the first voltage after the second detector detected the second detector.

Claims (39)

1. A reset circuit, comprising:

a first detector arranged to detect that a voltage of a power source has reached a predetermined first voltage;

a second detector arranged to detect that the voltage of the power source has reached a predetermined second voltage, the second voltage being lower than the first voltage; and

a controller arranged to control an output of a reset request signal based on detection results of the first detector and the second detector,

wherein the controller is configured to output the reset request signal when the first detector detects the first voltage after the second detector detected the second voltage, and

wherein the controller makes the first detector detectable after the second detector detected that a voltage of a backup capacitor connected to the power source became below the second voltage and makes an output from the first detector into the reset request signal.

2. The reset circuit as recited in claim 1 , wherein the controller is configured to receive a reset receipt signal and initialize the reset request signal to prohibit the reset request.

3. A reset circuit, comprising:

a first detector arranged to detect a predetermined first voltage of a power source;

a second detector arranged to detect a predetermined second voltage of the power source, the second voltage being lower than the first voltage; and

a controller arranged to control an output of a reset request signal based on detection results of the first detector and the second detector,

wherein the controller is configured to output the reset request signal when the first detector detects the first voltage after the second detector detected the second voltage,

wherein the second detector is constituted by an ADC circuit,

wherein the controller includes a register, and

wherein the ADC circuit is configured to output a reset enabling signal to set a permission flag in the register to permit changing of the reset request signal when the permission flag is set.

4. A reset circuit for an electronic circuit equipped with a power backup capacitor,

the reset circuit comprising:

a first detector arranged to detect a predetermined first voltage of the backup capacitor;

a second detector arranged to detect a predetermined second voltage of the backup capacitor, the second voltage being lower than the first voltage; and

a controller arranged to control an output of a reset request signal based on detection results of the first detector and the second detector,

wherein the controller is configured to output the reset request signal when the first detector detects the first voltage after the second detector detected the second voltage.

5. The reset circuit as recited in claim 4 , wherein the controller makes the first detector detectable after the second detector detected that a voltage of the backup capacitor became below the second voltage and makes an output from the first detector into the reset request signal.

6. The reset circuit as recited in claim 5 , wherein the controller is configured to receive a reset receipt signal and initialize the reset request signal to prohibit the reset request.

7. The reset circuit as recited in claim 4 ,

wherein the second detector is constituted by an ADC circuit,

wherein the controller includes a register, and

wherein the ADC circuit is configured to output a reset enabling signal to set a permission flag in the register to permit changing of the reset request signal when the permission flag is set.

8. An electronic circuit equipped with a backup operation circuit, a reset circuit, and a power backup capacitor,

the reset circuit comprising:

a first detector arranged to detect a predetermined first voltage of the backup capacitor;

a second detector arranged to detect a predetermined second voltage of the backup capacitor, the second voltage being lower than the first voltage; and

a reset controller arranged to control an output of a reset request signal based on detection results of the first detector and the second detector,

wherein the controller is configured to output the reset request signal to the backup operation circuit when the first detector detects the first voltage after the second detector detected the second voltage.

9. The reset circuit as recited in claim 8 , wherein the controller makes the first detector detectable after the second detector detected that a voltage of the backup capacitor became below the second voltage and makes an output from the first detector into the reset request signal.

10. The reset circuit as recited in claim 9 , wherein the controller is configured to receive a reset receipt signal and initialize the reset request signal to prohibit the reset request.

11. The reset circuit as recited in claim 8 ,

wherein the second detector is constituted by an ADC circuit,

wherein the controller includes a register, and

wherein the ADC circuit is configured to output a reset enabling signal to set a permission flag in the register to permit changing of the reset request signal when the permission flag is set.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT #12/577882 PREVIOUSLY RECORDED ON REEL 026594 FRAME 0385. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2014
From: SANYO ELECTRIC CO., LTD
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 032836/0342 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2013
From: SANYO SEMICONDUCTOR CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 031729/0866 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2011
From: SANYO ELECTRIC CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 026594/0385 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 6, 2010
From: YAMADA, SUSUMU
To: SANYO ELECTRIC CO., LTD.; SANYO SEMICONDUCTOR CO., LTD.
Reel/Frame 025099/0362 →
Priority Claims (1)
JP 2009-224993 · Sep 29, 2009 · national
Continuity (1)
Related Publication 20110074473A1 · Mar 31, 2011