Imaging systems and methods for providing a switchable impedance to ground

1. A method for reducing artifacts of an imaging system comprising:

configuring an imaging device of the imaging system with a switchable impedance configured to couple a ground ring of a pixel array of the imaging device to ground through the switchable impedance wherein the ground ring substantially encircles the pixel array;

configuring the switchable impedance to selectively couple the ground ring to ground through a high impedance level in response to a correlated double sampling (“CDS”) period of operation of the imaging system; and

configuring the switchable impedance to selectively couple the ground ring to ground through a low impedance level for an analog-to-digital conversion (“ADC”) period of operation of the imaging system.

2. The method of claim 1 , wherein:

the high impedance level comprises a value greater than 300 ohms; and

the low impedance level comprises a value less than 20 ohms.

3. The method of claim 1 , wherein configuring the imaging device includes configuring the pixel array comprising a plurality of pixel cells wherein each pixel cell of the plurality of pixel cells comprises a source follower transistor including a body; and

configuring the high impedance level comprising a resistance value sufficiently high to increase a body settling time of the source follower to a value that results in a negligible settling of the body of each pixel cell during the CDS period.

4. The method of claim 1 , wherein configuring the switchable impedance includes configuring the low impedance level comprising a resistance value sufficiently low such that drift of a ground reference level does not occur during the ADC period.

5. The method of claim 1 , wherein configuring the switchable impedance includes configuring the switchable impedance to form the high impedance level at substantially the same time the CDS period of operation begins.

6. The method of claim 1 , wherein configuring the switchable impedance includes configuring the switchable impedance to form the high impedance level during an enabling of a SHR command signal of the CDS period of operation.

7. The method of claim 1 , wherein

configuring the switchable impedance includes configuring the switchable impedance to form the low impedance level before the ADC readout period begins.

8. A method of forming an imaging device, comprising:

configuring the imaging device to couple a pixel array of the imaging device to ground via a switchable impedance;

configuring the imaging device to set the switchable impedance to a high impedance value;

configuring the imaging device to generate an output signal corresponding to at least one pixel cell of the pixel array, wherein the output signal corresponds to an amount of light sensed by the at least one pixel cell, wherein the high impedance value comprises a resistance value large enough to increase a body settling time of a transistor of the at least one pixel cell of the pixel array such that an insubstantial amount of body settling occurs while generating the output signal, and wherein the high impedance value is maintained substantially throughout generating the output signal;

configuring the imaging device to set the switchable impedance to a low impedance value; and

configuring the imaging device to convert the generated output signal from an analog signal to a digital signal, wherein the low impedance value comprises a resistance value small enough to prevent drift of a ground reference value during the converting, and wherein the low impedance value is maintained substantially throughout the converting.

9. The method of claim 8 , wherein the body settling comprising body settling of a source follower transistor of the at least one pixel cell.

10. The method of claim 8 , wherein generating the output signal comprises:

performing correlated double sampling on the at least one pixel cell.

11. The method of claim 8 , wherein generating the output value comprises:

receiving a reference level signal from the at least one pixel cell;

receiving a signal level signal from the at least one pixel cell; and

generating the output signal by subtracting the signal level signal from the reference level signal.

12. The method of claim 11 , wherein receiving the reference level signal comprises:

asserting a RST command signal to turn on a reset transistor of the at least one pixel cell; and

asserting a SHR command signal to sample and hold a signal that is output by the at least one pixel cell as a result of asserting the RST command signal.

13. The method of claim 11 , wherein receiving the signal level signal comprises:

asserting a TX control signal to turn on a transfer transistor of the at least one pixel cell, wherein the transfer transistor couples a light-sensing element of the at least pixel cell to a floating diffusion node of the at least one pixel cell; and

asserting a SHS command signal to sample and hold a signal that is output by the at least one pixel cell as a result of asserting the TX control signal.

14. The method of claim 8 , wherein configuring the imaging device to couple the pixel array of the imaging device to ground includes configuring the imaging device to couple a ground ring that substantially encircles the pixel array to ground via the switchable impedance, and wherein the at least one pixel cell comprises a row of pixel cells of the array.

15. An imaging system comprising:

a pixel array including a plurality of pixel cells arranged in rows and columns;

a ground ring coupled to and surrounding the pixel array, the ground ring coupled to ground nodes of the pixel array; and

a switchable impedance coupling the ground ring to a ground reference level, wherein the switchable impedance:

switches to a high impedance value for a pixel cell sampling phase of the pixel array, wherein the cell sampling phase generates at least one output signal corresponding to an amount of light sensed by at least one pixel cell of the pixel array; and

switches to a low impedance value for an analog-to-digital conversion (“ADC”) phase of the pixel array, wherein the ADC phase converts the at least one output signal from an analog value to a digital value.

16. The imaging system of claim 15 , further comprising:

an n-tub isolation layer positioned beneath the pixel array and intersecting the ground ring, wherein:

the n-tub isolation layer causes a body settling time of each pixel cell of the plurality of pixel cells to vary based on each pixel cell's relative distance from the center of the pixel array; and

the varying of the body settling time causes a black hole artifact in the pixel array.

17. The imaging system of claim 16 , wherein:

the high impedance value increases the body settling time to a value that results in an insignificant amount of body settling of each pixel cell occurs during the pixel cell sampling phase.

18. The imaging system of claim 15 , further comprising:

an n-tub isolation layer positioned beneath the pixel array;

an n-tub of n-type material positioned beneath the n-tub isolation layer; and

a pixel power ring encircling the pixel array and coupled to the n-tub, wherein the pixel power ring positively biases the n-tub such that the n-tub prevents deeply generated electrons from reaching the pixel array.

19. The imaging system of claim 15 , wherein the high impedance value comprises a value greater than 500 ohms, and the low impedance value comprises a value less than 10 ohms.

20. The imaging system of claim 15 , wherein each pixel cell is formed to have a body settling time and wherein the high impedance value increases the body settling time to a value that results in an insignificant amount of body settling occurring for each pixel cell during a time that the pixel cell sampling phase occurs.