Damascene method of forming a semiconductor structure and a semiconductor structure with multiple fin-shaped channel regions having different widths
View Patent ↗Disclosed is a damascene method for forming a semiconductor structure and the resulting semiconductor structure having multiple fin-shaped channel regions with different widths. In the method, fin-shaped channel regions are etched using differently configured isolating caps as masks to define the different widths. For example, a wide width isolating cap can comprise a dielectric body positioned laterally between dielectric spacers and can be used as a mask to define a relatively wide width channel region; a medium width isolating cap can comprise a dielectric body alone and can be used as a mask to define a medium width channel region and/or a narrow width isolating cap can comprise a dielectric spacer alone and can be used as a mask to define a relatively narrow width channel region. These multiple fin-shaped channel regions with different widths can be incorporated into either multiple multi-gate field effect transistors (MUGFETs) or a single MUGFET.
1. A method of forming a semiconductor structure, said method comprising:
forming a trench isolation structure to define, in a semiconductor layer, a first semiconductor region and a second semiconductor region positioned laterally adjacent to said first semiconductor region;
forming a first dielectric body on said first semiconductor region and a second dielectric body on said second semiconductor region;
forming first dielectric spacers on first opposing sides of said first dielectric body;
forming a sacrificial layer traversing a first center portion of said first semiconductor region over said first dielectric body and said first dielectric spacers and also traversing a second center portion of said second semiconductor region over said second dielectric body;
depositing a blanket dielectric layer so as to cover first end portions of said first semiconductor region and second end portions of said second semiconductor region;
planarizing said dielectric layer to expose said sacrificial layer;
selectively removing said sacrificial layer;
performing a directional etch process to remove exposed semiconductor material within said first center portion and said second center portion such that, after said performing of said directional etch process, said first center portion has a first width and said second center portion has a second width that is less than said first width.
2. The method of claim 1 , further comprising:
during said forming of said first dielectric spacers also forming second dielectric spacers on second opposing sides of said second dielectric body; and
after said forming of said first dielectric spacers and said second dielectric spacers, selectively removing said second dielectric spacers.
3. The method of claim 1 , said directional etch process being performed using, as masks, said dielectric layer on said first end portions and said second end portions, said first dielectric body and said first dielectric spacers on said first center portion and said second dielectric body on said second center portion.
4. The method of claim 1 ,
said first dielectric body and said second dielectric body being formed with a first dielectric material and
said first dielectric spacers and said second dielectric spacers being formed with a second dielectric material different from said first dielectric material.
5. The method of claim 1 , further comprising, after said performing of said directional etch process, forming a gate structure on exposed first sidewalls of said first center portion and on exposed second sidewalls of said second center portion.
6. The method of claim 5 , further comprising, before said forming of said gate structure, selectively removing dielectric material from above at least one of said first center portion and said second center portion.
7. A method of forming a semiconductor structure, said method comprising:
forming a trench isolation structure to define, in a semiconductor layer, a first semiconductor region and a second semiconductor region positioned laterally adjacent to said first semiconductor region;
forming a first dielectric body on said first semiconductor region and a second dielectric body on said second semiconductor region;
forming first dielectric spacers on first opposing sides of said first dielectric body and second dielectric spacers on second opposing sides of said second dielectric body;
selectively removing said second dielectric body;
forming a sacrificial layer traversing a first center portion of said first semiconductor region over said first dielectric body and said first dielectric spacers and also traversing a second center portion of said second semiconductor region over said second dielectric spacers;
depositing a blanket dielectric layer so as to cover first end portions of said first semiconductor region and second end portions of said second semiconductor region;
planarizing said dielectric layer to expose said sacrificial layer;
selectively removing said sacrificial layer;
performing a directional etch process to remove exposed semiconductor material within said first center portion and said second center portion such that, after said performing of said directional etch process, said first center portion has a first width and said second center portion comprises two parallel sections, each of said parallel sections having a second width that is less than said first width.
8. The method of claim 7 , said directional etch process being performed using, as masks, said dielectric layer on said first end portions and said second end portions, said first dielectric body and said first dielectric spacers on said first center portion and said second dielectric spacers on said second center portion.
9. The method of claim 7 ,
said first dielectric body and said second dielectric body being formed with a first dielectric material,
said first dielectric spacers and said second dielectric spacers being formed with a second dielectric material different from said first dielectric material.
10. The method of claim 7 , further comprising: after said performing of said directional etch process, forming a gate structure on first sidewalls of said first center portion and on second sidewalls of said parallel sections of said second center portion.