Ni-P layer system and process for its preparation

1. A process for the preparation of a layer system comprising on a substrate

(i) a Ni layer having a thickness ≦3.0 μm,

(ii) a Ni—P layer having a thickness ≦1.0 μm,

(iii) a Au layer ≦1.0 μm

comprising the following steps:

(i) electropolishing the surface of said substrate,

(ii) plating a Ni layer onto the electropolished surface obtained in step (i) above such that the thickness of said Ni layer is ≦3.0 μm,

(iii) plating a Ni—P layer onto the Ni layer obtained in step (ii) above such that the thickness of said Ni—P layer is ≦1.0 μm,

(iv) plating an Au layer onto the Ni—P layer obtained in step (iii) above such that the thickness of said Au layer is ≦1.0 μm.

2. The process according to claim 1 , further comprising the steps of

(v) hot degreasing,

(vi) cathodic degreasing and

(vii) acid rinsing

prior to the electropolishing step (i).

3. The process according to claim 1 wherein the Ni layer is plated with a thickness of 1.0 to 2.0 μm onto the electropolished surface.

4. The process according to claim 1 , further comprising

(viii) the step of treating the layer system with a post dip after step (iv).

5. An electronic device substrate comprising the layer system obtained by the process according to claim 1 .

6. The electronic device substrate according to claim 5 which is a lead line of an electronic component.

7. The electronic device substrate according to claim 6 which is a lead line of a lead frame, an electrical connector, an electrical contact or a passive component.

8. The electronic device substrate according to claim 7 wherein the passive component is a chip capacitor or a chip resistor.

9. The process according to claim 1 wherein the substrate comprises a copper-based substrate.

10. The process according to claim 1 wherein the Ni—P layer has a thickness in the range of 0.05 μm to 0.80 μm.

11. The process according to claim 10 wherein the Ni—P layer has a thickness in the range of 0.1 μm to 0.40 μm.

12. A process according to claim 1 wherein the Ni layer has a thickness of 1.0 to 2.0 μm.

13. The process according to claim 1 wherein the layer system has been treated with a post dip.

14. The process according to claim 1 wherein the Ni—P layer (i) has a phosphorous content of 3 to 25 wt.-%.

15. The process according to claim 1 wherein the Au layer further comprises an element selected from the group consisting of Fe, Co and Ni.