FinFET transistor with high-voltage capability and CMOS-compatible method for fabricating the same
View Patent ↗The present invention relates to a method for fabricating a FinFET on a substrate. The method comprises providing a substrate with an active semiconductor layer on an insulator layer, and concurrently fabricating trench isolation regions in the active semiconductor layer for electrically isolating different active regions in the active semiconductor layer from each other, and trench gate-isolation regions in the active semiconductor layer for electrically isolating at least one gate region of the FinFET in the active semiconductor layer from a fin-shaped channel region of the FinFET in the active semiconductor layer.
1. A method for fabricating a FinFET on a substrate, comprising:
providing a substrate with an active semiconductor layer on an insulator layer; and
concurrently fabricating
a) trench isolation regions in the active semiconductor layer for electrically isolating different active regions in the active semiconductor layer from each other, and
b) trench gate-isolation regions in the active semiconductor layer for electrically isolating at least one gate region of the FinFET in the active semiconductor layer from a fin-shaped channel region of the FinFET in the active semiconductor layer;
wherein concurrently fabricating the trench isolation regions and the trench gate-isolation regions comprises:
fabricating first trenches in the active semiconductor layer for the trench isolation regions and second trenches in the active semiconductor layer for the trench gate-isolation regions; and
filling the first trenches and the second trenches with an insulating material, thus providing the trench isolation regions and the trench gate-isolation regions.
2. The method of claim 1 , wherein concurrently fabricating the trench isolation regions and the trench gate-isolation regions is performed employing a lithographic process with a single mask for defining the trench isolation regions and the trench gate-isolation regions.
3. The method of claim 1 , wherein providing the substrate with the active semiconductor layer comprises fabricating a silicon or a silicon-germanium layer on the insulator layer.
4. The method of claim 1 , wherein filling the first and second trenches comprises depositing silicon dioxide, silicon nitride, silicon oxynitride, or a layer structure made of a combination of two or more of these materials.
5. The method of claim 1 , further comprising fabricating in the active semiconductor layer, in at least two masked doping processes,
a well region and the fin-shaped channel region, both of a first conductivity type, and
source and drain regions on either side of the fin-shaped channel region, both of a second conductivity type opposite to the first conductivity type.
6. The method of claim 5 , further comprising:
fabricating a fin-shaped extended-drain region between the fin-shaped channel region and the drain region, the extended-drain region having the second conductivity type but a lower active dopant concentration per volume than the drain region.
7. The method of claim 6 , further comprising:
fabricating trench field-plate isolation regions concurrently with the trench isolation regions and the trench gate-isolation regions, and
fabricating electrically conductive field plates on both lateral sides of the fin-shaped extended-drain region, wherein
together with the first and second trenches, third trenches are fabricated in the active semiconductor layer on both lateral sides of the fin-shaped extended-drain region for defining field-plate isolation regions.
8. The method of claim 1 , further comprising:
fabricating two separate gate regions isolated from each other, one on each side of the fin-shaped channel region.
9. The method of claim 1 , further comprising:
fabricating a single gate region on one of the two lateral sides of the fin-shaped channel region.
10. A method for fabricating an integrated circuit, comprising fabricating a FinFET according to the method of claim 1 .
11. A FinFET, comprising:
a substrate with an active semiconductor layer on an insulator layer;
a fin-shaped channel region extending between a source region and a drain region in the active semiconductor layer;
at least one gate region in the active semiconductor layer;
trench isolation regions filling first trenches in the active semiconductor layer, for electrically isolating different active regions in the active semiconductor layer from each other; and
trench gate-isolation regions filling second trenches in the active semiconductor layer for electrically isolating the at least one gate region of the FinFET in the active semiconductor layer from the fin-shaped channel region of the FinFET in the active semiconductor layer;
wherein the trench isolation regions and the trench-gate isolation regions are connected, together form a continuous trench isolation structure, and are of the same material with no interface between the trench isolation regions and the trench-gate isolation regions.
12. The FinFET of claim 11 , wherein the first trenches of the trench isolation regions and the second trenches of the trench gate-isolation regions have trench widths between opposite trench walls differing by at most 50 nanometers.
13. The FinFET of claim 11 , further comprising a fin-shaped extended-drain region between the fin-shaped channel region and the drain region, the extended-drain region having the second conductivity type but a lower active dopant concentration per volume than the drain region.
14. The FinFET of claim 13 , further comprising:
electrically conductive field plates on both lateral sides of the fin-shaped extended-drain region, and
trench field-plate isolation regions isolating the fin-shaped extended drain regions from the field plates.
15. The FinFET of claim 11 , wherein the trench isolation region isolates the source region and the drain region of the FinFET from source and drain regions of laterally neighboring FinFETs.
16. The FinFET of claim 11 , wherein the width of the trench isolation regions and the width of the trench-gate isolation regions are identical.
17. The method of claim 1 , further comprising fabricating in the active semiconductor layer:
a well region and the fin-shaped channel region; and
a source region and a drain region, the fin-shaped channel region extending between the source region and the drain region;
wherein the trench isolation region isolates the source region and the drain region of the FinFET from source and drain regions of laterally neighboring FinFETs; and
wherein the at least one gate region is laterally adjacent to the fin-shaped channel region and is isolated from the fin-shaped channel region by the trench-gate isolation region.
18. The method of claim 17 , wherein concurrently fabricating the trench isolation regions and the trench gate-isolation regions comprises:
fabricating first trenches in the active semiconductor layer for the trench isolation regions and second trenches in the active semiconductor layer for the trench gate-isolation regions; and
concurrently filling the first trenches and the second trenches with an insulating material, thus providing the trench isolation regions and the trench gate-isolation regions.
19. The method of claim 18 , wherein the channel region, the source region, and the drain region are fabricated in masked doping processes, wherein the trench isolation regions and the trench-gate isolation regions are concurrently fabricated prior to the fabrication of the channel region, the source region, and the drain region with the masked doping processes.