Granted Patent B2

US 7,939,416 · App. 12/935,924 · Granted May 10, 2011

Abstract

Claims (29)

1. A method of manufacturing a bipolar transistor, comprising

defining a collector region of semiconductor having a central region longitudinally between end regions;

forming an insulating layer on the lateral sidewalls and top of the collector region in the central region;

forming base contact regions on both lateral sides of the collector region in the central region;

forming a gap between the tops of the base contact regions, the gap exposing the collector region in the central region;

depositing a base semiconductor layer on the exposed collector region in the gap, on the sidewalls of the gap and the tops of the polysilicon base contact region adjacent to the gap;

forming spacers on the lateral inside edges of the base semiconductor layer in the gap; and

filling the gap with an emitter semiconductor layer.

2. A method according to claim 1 wherein forming the collector region includes forming the collector region to have a plurality of trenches extending longitudinally between the end region and the central region.

3. A method according to claim 1 wherein the step of forming a collector region includes:

providing a silicon layer on a substrate;

depositing and patterning a hard mask over the silicon layer, and

etching through the full thickness of the silicon layer using the hard mask as a mask to define the collector region.

4. A method according to claim 3 further comprising, after forming the base contact regions, planarising the base contact regions;

wherein the step of forming a gap includes etching away the insulating layer on the hard mask and the hard mask between the base contact regions.

5. A method according to claim 3 wherein the step of providing a silicon layer on a substrate includes providing a silicon layer on an insulating layer on a substrate.

6. A method according to claim 1 wherein the step of filling the gap with an emitter layer of semiconductor includes:

depositing an emitter layer of semiconductor over the surface and between the spacers; and

etching back the semiconductor of the emitter layer leaving the emitter layer only between the spacers.

7. A method according to claim 1 further comprising forming a collector contact on the collector layer in the end regions, a base contact on the base contact regions and an emitter contact on the emitter layer.

8. A method according to claim 1 wherein forming the base contact regions includes:

depositing a conducting layer over the insulating layer at least in the central region;

etching back the conducting layer to expose the insulating layer on the top of the collector region in the central region leaving the polysilicon base contact regions on both lateral sides of the collector region.

9. A method according to claim 8 wherein the conducting layer is of polysilicon.

10. A method according to claim 1 wherein the step of defining the collector region defines the collector region to have a lateral width in the range 150 μm to 400 μm in the central region.

11. A method according to claim 1 further comprising forming a finFET in the same process, wherein:

the step of defining a collector region of semiconductor also defines the fin of the finFET; and

the step of forming base contact regions on both lateral sides of the collector region in the central region also forms the gate of the finFET.

12. A method according to claim 11 wherein the step of forming an insulating layer on the lateral sidewalls and top of the collector region in the central region also forms the gate insulator of the finFET.

Assignments (14)