Method for copper hillock reduction
A method of forming interconnects in integrated circuits includes providing a semiconductor substrate and forming a copper interconnect structure that is formed overlying a barrier layer within a thickness of an interlayer dielectric layer. The copper interconnect structure has a first stress characteristic. The method further loads the semiconductor substrate including the copper interconnect structure into a deposition chamber that contains an inert environment. The semiconductor substrate including the copper interconnect structure is annealed in the inert environment for a period of time to cause the copper interconnect structure to have a second stress characteristic. The semiconductor substrate is maintained in the deposition chamber while an etch stop layer is deposited thereon. The method further deposits an intermetal dielectric layer overlying the etch stop layer, wherein the annealing reduces copper hillock defects resulting from at least the first stress characteristic.
1. A method of forming interconnects in integrated circuits (IC), comprising:
providing a semiconductor substrate having one or more IC devices formed thereon;
forming a copper interconnect structure, the copper interconnect structure being formed overlying an oxide on nitride on oxide barrier layer within a thickness of an interlayer dielectric layer, the copper interconnect structure having a first stress characteristic;
loading the semiconductor substrate including the copper interconnect structure into a deposition chamber;
providing an inert environment within the deposition chamber;
subjecting the semiconductor substrate including the copper interconnect structure to an anneal process in the inert environment for a period of time to cause the copper interconnect structure to have reduced copper hillock defects;
maintaining the semiconductor substrate in the deposition chamber; and
depositing an etch stop layer overlying the copper interconnect structure; and
depositing an inter-metal dielectric layer overlying the etch stop layer,
wherein the anneal process is characterized by:
a pressure ranging from about 2 Torr to about 10 Torr;
a temperature ranging from about 320 degree Celsius to about 360 degree Celsius; and
the period of time ranging from about 30 seconds to about 200 seconds.
2. The method of claim 1 , wherein the inter-metal dielectric layer is a low k dielectric material.
3. The method of claim 1 , wherein the inter-metal dielectric layer comprises silicon oxide, doped silicon oxide, organo silicon oxide, carbon doped silicon oxide, or nitrogen doped carbide (NDC).
4. The method of claim 1 , wherein the inert environment is provided by nitrogen, argon, helium, or a combination thereof.
5. The method of claim 1 , wherein the deposition chamber is a chemical vapor deposition chamber.
6. The method of claim 5 , wherein the deposition chamber is a plasma enhanced chemical vapor deposition chamber.
7. The method of claim 1 , wherein the etch stop layer is deposited by a plasma enhanced chemical vapor deposition process.
8. The method of claim 1 , wherein the etch stop layer is deposited at a temperature within a range of the temperature of the anneal process.
9. The method of claim 1 , wherein the first stress characteristic causes a plurality of copper hillock defects.
10. The method of claim 1 , wherein the plurality of copper hillock defects is measured after deposition of the inter-metal dielectric layer.
11. The method of claim 1 , wherein the etch stop layer comprises silicon nitride, silicon carbonitride (SiCN), or a combination thereof.
12. A method of forming interconnects in integrated circuits, comprising:
providing a semiconductor substrate having one or more devices providing thereon;
forming a copper interconnect structure, the copper interconnect structure being formed overlying an oxide on nitride on oxide barrier layer within a thickness of an interlayer dielectric layer, the copper interconnect structure comprising a first stress characteristic;
loading the semiconductor substrate including the copper interconnect structure into a deposition chamber;
providing an inert environment within the deposition chamber;
subjecting the semiconductor substrate including the copper interconnect structure to an anneal process in the inert environment for a period of time to cause the copper interconnect structure to have reduced copper hillock defects;
maintaining the semiconductor substrate in the deposition chamber;
depositing a dielectric layer overlying the copper interconnect structure; and
depositing an inter-metal dielectric layer overlying the dielectric layer,
wherein the anneal process is further characterized by:
a pressure ranging from about 2 Torr to about 10 Torr;
a temperature ranging from about 320 degree Celsius to about 360 degree Celsius; and
the period of time ranging from about 30 seconds to about 200 seconds.
13. The method of claim 12 , wherein the inter-metal dielectric layer comprises a low k dielectric material, the low k dielectric material is selected from the group: silicon oxide, doped silicon oxide, organo silicon oxide, carbon doped silicon oxide, and nitrogen doped carbide (NDC).
14. The method of claim 12 , wherein the dielectric layer is an etch stop layer comprising silicon nitride, silicon carbonitride (SiCN), or a combination thereof and being deposited at a temperature within a range of the temperature of the anneal process.
15. The method of claim 12 , wherein the copper hillock defects are measured after deposition of the inter-metal dielectric layer.
16. The method of claim 1 , wherein the pressure is maintained using argon at a flow rate of about 2000 SCCM.