Butted SOI junction isolation structures and devices and method of fabrication

1. A method, comprising:

providing a silicon layer on a buried oxide layer of a silicon-on-insulator substrate;

forming a first gate electrode of a first field effect transistor on a top surface of a gate dielectric layer formed on a top surface of said silicon layer and forming a second gate of a second field effect transistor on said top surface of said gate dielectric layer;

etching a trench in said silicon layer between said first and second gate electrodes, said trench extending from a top surface of said silicon layer into said silicon layer, said trench not extending to said buried oxide layer;

ion implanting a dopant species into said silicon layer under a bottom of said trench to form a first doped region in said silicon layer, said first doped region doped to a first concentration;

performing a first epitaxial deposition to form a first epitaxial layer doped to a second concentration in said bottom of said trench, said first epitaxial layer partially filling said trench;

performing a second epitaxial deposition to form a second epitaxial layer doped to a third concentration on said first epitaxial layer in said trench; and

wherein said third concentration is greater than said first and second concentrations and said first concentration is greater than said second concentration.

2. The method of claim 1 , wherein after said ion implanting said doped region, said doped region abuts said buried oxide layer.

3. The method of claim 1 , including:

after said ion implanting said doped region and before forming said first epitaxial silicon layer, said doped region does not abut said buried oxide layer.

4. The method of claim 1 , wherein:

(i) said doped region, said first epitaxial layer and said second epitaxial layer are all doped a same dopant type; or

(ii) said doped region and said first epitaxial layer are doped a first dopant type and said second epitaxial layer is doped a second and opposite dopant type; or

(iii) said doped region and said first epitaxial layer are doped a first dopant type and said second epitaxial layer is net doped zero or is intrinsic.

5. The method of claim 1 , further including:

ion implanting a dopant species into an upper region of said second epitaxial layer to form an additional doped region doped to a fourth dopant concentration, said additional doped region extending from a top surface of said second epitaxial layer into said second epitaxial layer a distance less than the thickness of said second epitaxial layer, said fourth dopant concentration greater than said third dopant concentration.

6. The method of claim 5 , wherein:

(i) said additional doped region, said first epitaxial layer and said second epitaxial layer are all doped a same dopant type; or

(ii) said doped region, said additional doped region and said first epitaxial layer are doped a first dopant type and said second epitaxial layer is doped a second and opposite dopant type; or

(iii) said doped region, said additional doped region and said first epitaxial layer are doped a first dopant type and said second epitaxial layer is net doped zero or is intrinsic.

7. The method of claim 5 , further including:

before etching said trench in said silicon layer and after forming said gate dielectric layer and said first and second gate electrodes, ion implanting first source/drain extensions on opposite sides of said first gate electrode into said silicon layer and ion implanting second source/drain extensions on opposite sides of second gate electrode, said first source/drain extensions extending under said first gate electrode and separated by a first channel region of said silicon layer under said gate electrode, said second source/drain extensions extending under said second gate electrode and separated by a second channel region of said silicon layer, said first and said second source/drain extensions doped said first dopant type.

8. The method of claim 5 , further including:

after performing said second epitaxial layer, ion-implanting a first source/drain of said first field effect transistor and a shared source/drain of said first and second field effect transistors and a second source/drain of said second field effect transistor into an upper region of said second epitaxial layer, said first, common and second source/drains doped to a fourth dopant concentration, said first, common and second source/drains doped said first dopant type, said first, common and second source/drains extending from a top surface of said second epitaxial layer into said second epitaxial layer a distance less than the thickness of said second epitaxial layer, said fourth dopant concentration greater than said third dopant concentration.

9. The method of claim 8 , wherein said second epitaxial layer does not contribute any P-type dopant species to depletion layers of said first, said common and said second source/drains.

10. The method of claim 1 , wherein after forming said second epitaxial layer and performing an anneal of greater than room temperature an electrically resistive channel is formed in a region of said first epitaxial layer, said electrically resistive channel physically connecting a first region of said silicon layer under said first gate electrode to a second region of said silicon laser under said second gate electrode.

11. The method of claim 5 , wherein after forming said second epitaxial layer and performing an anneal of greater than room temperature an electrically resistive channel is formed in a region of said first epitaxial layer, said electrically resistive channel physically connecting a first region of said silicon layer under said first gate electrode to a second region of said silicon laser under said second gate electrode.

12. The method of claim 1 , wherein said first epitaxial layer includes silicon and includes germanium.

13. The method of claim 1 , wherein said first epitaxial layer includes silicon and includes carbon.

14. The method of claim 1 , wherein-said second epitaxial layer includes silicon and excludes other group IV atoms.

15. The method of claim 1 , wherein said second epitaxial layer includes silicon and includes germanium.

16. The method of claim 1 , wherein said second epitaxial layer includes silicon and includes carbon.

17. The method of claim 5 , wherein after forming said second epitaxial layer and performing an anneal of greater than room temperature an electrically resistive channel is formed in a region of said first epitaxial layer, said electrically resistive channel physically connecting a first region of said silicon layer under said first gate electrode to a second region of said silicon laser under said second gate electrode, and after said anneal when said first epitaxial layer is doped N-type while said electrically resistive channel is doped N-type it is depleted of electrons and behaves electrically as a P-type doped region and when said first epitaxial layer is doped P-type while said electrically resistive channel is doped P-type it is depleted of holes and behaves electrically as an N-type doped region.

18. The method of claim 1 , wherein said first epitaxial layer includes silicon and excludes other group IV atoms.

19. The method of claim 1 further including:

before etching said trench in said silicon layer and after forming said gate dielectric layer and said first and second gate electrodes, ion implanting first source/drain extensions on opposite sides of said first gate electrode into said silicon layer and ion implanting second source/drain extensions on opposite sides of second gate electrode, said first source/drain extensions extending under said first gate electrode and separated by a first channel region of said silicon layer under said gate electrode, said second source/drain extensions extending under said second gate electrode and separated by a second channel region of said silicon layer, said first and said second source/drain extensions doped said first dopant type.

20. The method of claim 1 , further including:

after performing said second epitaxial layer, ion-implanting a first source/drain of said first field effect transistor and a shared source/drain of said first and second field effect transistors and a second source/drain of said second field effect transistor into an upper region of said second epitaxial layer, said first, said common and said second source/drains doped to a fourth dopant concentration, said first, said common and said second source/drains doped said first dopant type, said first, said common and said second source/drains extending from a top surface of said second epitaxial layer into said second epitaxial layer a distance less than the thickness of said second epitaxial layer, said fourth dopant concentration greater than said third dopant concentration.

21. The method of claim 20 , wherein said second epitaxial layer does not contribute any P-type dopant species to depletion layers of said first, said common and said second source/drains.

22. The method of claim 1 , wherein after forming said second epitaxial layer and performing an anneal of greater than room temperature an electrically resistive channel is formed in a region of said first epitaxial layer, said electrically resistive channel physically connecting a first region of said silicon layer under said first gate electrode to a second region of said silicon laser under said second gate electrode, and after said anneal when said first epitaxial layer is doped N-type while said electrically resistive channel is doped N-type it is depleted of electrons and behaves electrically as a P-type doped region and when said first epitaxial layer is doped P-type while said electrically resistive channel is doped P-type it is depleted of holes and behaves electrically as an N-type doped region.