Input/output core design and method of manufacture therefor
View Patent ↗One aspect provides an input/output cell. The input/output cell, in one example, includes an input/output layout boundary delineated on a substrate, wherein the input/output layout boundary defines a first side parallel and opposing a second side, a third side parallel and opposing a fourth side, wherein the first and second sides are substantially perpendicular the third and fourth sides. The input/output cell, in this example, further includes input/output transistors positioned within the input/output layout boundary over the substrate. The input/output cell, in this example, further includes first and second power conductors and first and second ground conductors located over the substrate, the first power conductor and first ground conductor extending entirely between the first and second sides and the second power conductor and second ground conductor extending entirely between the third and fourth sides.
1. An integrated circuit chip, comprising:
core logic circuitry positioned over a substrate and within a core logic layout boundary delineated on the substrate; and
an array of input/output cells substantially surrounding and abutting the core logic layout boundary, each of the input/output cells including input/output transistors oriented in a same direction as the other input/output transistors in the array, each input/output cell further comprising:
an input/output layout boundary delineated on the substrate, wherein the input/output layout boundary defines a first side parallel and opposing a second side, a third side parallel and opposing a fourth side, wherein the first and second sides are substantially perpendicular the third and fourth sides;
first and second power conductors located over the substrate, the first power conductor extending entirely between the first and second sides and the second power conductor extending entirely between the third and fourth sides;
first and second ground conductors located over the substrate, the first ground conductor extending entirely between the first and second sides and the second ground conductor extending entirely between the third and fourth sides; and
a bond pad located within the input/output layout boundary over the substrate.
2. The integrated circuit chip recited in claim 1 , wherein each bond pad of each input/output cell is positioned proximate a single corner of its input/output layout boundary, and further wherein at least two edges of each bond pad of each input/output cell are facing the input/output transistors positioned within its input/output layout boundary.
3. The integrated circuit chip recited in claim 1 , wherein the input/output layout boundary of each input/output cell in the array forms a square.
4. The integrated circuit chip recited in claim 1 , wherein each input/output cell further includes a first signal pin located proximate a side of the input/output layout boundary abutting the core logic layout boundary, and a second signal pin located proximate a side perpendicular the side of the input/output layout boundary abutting the core logic layout boundary.
5. The integrated circuit chip recited in claim 1 , wherein the array is a first array, and further including a second array of the input/output cells substantially surrounding an exterior boundary of the first array.
6. The integrated circuit chip recited in claim 1 , wherein each bond pad is square.
7. The integrated circuit chip recited in claim 6 , wherein two edges of each bond pad face the input/output transistors.
8. The integrated circuit chip recited in claim 6 , wherein each bond pad is positioned proximate a corner of the input/output layout boundary.
9. The integrated circuit chip recited in claim 1 , wherein the input/output layout boundary of each input/output cell in the array forms a rectangle.
10. The integrated circuit chip recited in claim 1 , wherein input/output cells are not located at the corners of the integrated circuit chip.
11. A method for manufacturing an integrated circuit chip, comprising:
positioning core logic circuitry over a substrate and within a core logic layout boundary delineated on the substrate; and
forming an array of input/output cells, the array of input/output cells substantially surrounding and abutting the core logic layout boundary, each of the input/output cells including input/output transistors oriented in a same direction as the other input/output transistors in the array, each input/output cell further comprising:
an input/output layout boundary delineated on the substrate, wherein the input/output layout boundary defines a first side parallel and opposing a second side, a third side parallel and opposing a fourth side, wherein the first and second sides are substantially perpendicular the third and fourth sides;
first and second power conductors located over the substrate, the first power conductor extending entirely between the first and second sides and the second power conductor extending entirely between the third and fourth sides;
first and second ground conductors located over the substrate, the first ground conductor extending entirely between the first and second sides and the second ground conductor extending entirely between the third and fourth sides; and
a bond pad located within the input/output layout boundary over the substrate.
12. The method recited in claim 11 , wherein each bond pad of each input/output cell is positioned proximate a single corner of its input/output layout boundary, and further wherein at least two edges of each bond pad of each input/output cell are facing the input/output transistors positioned within its input/output layout boundary.
13. The method recited in claim 11 , wherein the input/output layout boundary of each input/output cell in the array forms a square.
14. The method recited in claim 11 , wherein each input/output cell further includes a first signal pin located proximate a side of the input/output layout boundary abutting the core logic layout boundary, and a second signal pin located proximate a side perpendicular the side of the input/output layout boundary abutting the core logic layout boundary.
15. The method recited in claim 11 , wherein the array is a first array, and further including a second array of the input/output cells substantially surrounding an exterior boundary of the first array.
16. The method recited in claim 11 , wherein each bond pad is square.
17. The method recited in claim 16 , wherein two edges of each bond pad face the input/output transistors.
18. The method recited in claim 16 , wherein each bond pad is positioned proximate a corner of the input/output layout boundary.
19. The method recited in claim 11 , wherein the input/output layout boundary of each input/output cell in the array forms a rectangle.
20. The method recited in claim 11 , wherein input/output cells are not located at the corners of the integrated circuit chip.