Single event transient direct measurement methodology and circuit
View Patent ↗A circuit and method of directly measuring the Single Event Transient (SET) performance of a combinatorial circuit includes a measurement chain. The measurement chain includes a plurality of cells, each in turn including a pair of SR latches, a dual-input inverter, and a target. During measurement and testing, the targets are irradiated, and a pulse signal caused by an SET event is allowed to propagate through the measurement chain only if the pair of SR latches are active at the same time. The pulse signal is latched by the measurement chain, thus allowing the presence of an SET event to be detected.
1. A Single Event Transient (SET) measurement circuit comprising:
a first SR latch coupled to a set input and a reset input;
a second SR latch coupled to the set input and the reset input;
a dual-input inverter having a first input coupled to an output of the first SR latch, a second input coupled to an output of the second SR latch, and an output; and
a target having an input coupled to the output of the dual-input inverter, and an output;
wherein the dual-input inverter comprises: a first P-channel transistor having a gate coupled to the first input; a second P-channel transistor having a gate coupled to the second input; a first N-channel transistor having a gate coupled to the first input; and a second N-channel transistor having a gate coupled to the second input.
2. The circuit of claim 1 wherein the target comprises a NAND gate.
3. The circuit of claim 1 wherein the target comprises an inverter.
4. The circuit of claim 1 wherein the target comprises a buffer.
5. A Single Event Transient (SET) measurement circuit comprising a plurality of serially coupled measurement cells, each cell comprising:
a first SR latch coupled to a set input and an output of a previous cell;
a second SR latch coupled to the set input and the output of the previous cell;
a dual-input inverter having a first input coupled to an output of the first SR latch, a second input coupled to an output of the second SR latch, and an output; and
a target having an input coupled to the output of the dual-input inverter, and an output forming the output of the cell;
wherein the dual-input inverter comprises: a first P-channel transistor having a gate coupled to the first input; a second P-channel transistor having a gate coupled to the second input; a first N-channel transistor having a gate coupled to the first input; and a second N-channel transistor having a gate coupled to the second input.
6. The circuit of claim 5 wherein the target comprises a NAND gate.
7. The circuit of claim 5 wherein the target comprises an inverter.
8. The circuit of claim 5 wherein the target comprises a buffer.
9. A Single Event Transient (SET) measurement circuit comprising:
a first SR latch coupled to a set input and a reset input;
a second SR latch coupled to the set input and the reset input;
a first dual-input inverter having a first input coupled to an output of the first SR latch, a second input coupled to an output of the second SR latch, and an output;
a plurality of targets having an input coupled to the output of the first dual-input inverter, and an output; and
a plurality of second dual-input inverters each having a first input coupled to the output of a respective target, a second input for receiving an enable signal, and an output;
wherein at least one of the dual-input inverters comprises: a first P-channel transistor having a gate coupled to the first input; a second P-channel transistor having a gate coupled to the second input; a first N-channel transistor having a gate coupled to the first input; and a second N-channel transistor having a gate coupled to the second input.
10. The circuit of claim 9 wherein at least one target comprises a NAND gate.
11. The circuit of claim 9 wherein at least one target comprises an inverter.
12. The circuit of claim 9 wherein at least one target comprises a buffer.
13. A Single Event Transient (SET) measurement circuit comprising a plurality of serially coupled measurement cells, each cell comprising:
a first SR latch coupled to a set input and an output of a previous cell;
a second SR latch coupled to the set input and the output of the previous cell;
a first dual-input inverter having a first input coupled to an output of the first SR latch, a second input coupled to an output of the second SR latch, and an output;
a plurality of targets having an input coupled to the output of the first dual-input inverter, and an output; and
a plurality of second dual-input inverters each having a first input coupled to the output of a respective target, a second input for receiving an enable signal, and an output, the coupled outputs of the plurality of second dual-input inverters forming the output of the cell;
wherein at least one of the dual-input inverters comprises: a first P-channel transistor having a gate coupled to the first input; a second P-channel transistor having a gate coupled to the second input; a first N-channel transistor having a gate coupled to the first input; and a second N-channel transistor having a gate coupled to the second input.
14. The circuit of claim 13 wherein at least one of the targets comprises a NAND gate.
15. The circuit of claim 13 wherein at least one of the targets comprises an inverter.
16. The circuit of claim 13 wherein at least one of the targets comprises a buffer.