Method for forming through-base wafer vias for fabrication of stacked devices
View Patent ↗An effective chemical mechanical planarization (CMP) method is provided for forming vias in silicon wafers for the fabrication of stacked devices using TSV (through-silicon via) technology. The method affords high removal rates of both metal (e.g., copper) and silicon such that a need for a grinding step prior to CMP processing may not be necessary. The method affords an approximately 1:1 Cu:Si selectivity for removal of silicon and copper under appropriate conditions and the Cu:Si selectivity is tunable by adjustment of levels of some key components.
1. A method for preparing a base silicon wafer for constructing an assembly comprising at least two integrated circuit chips at least one of which is from the base silicon wafer, said method comprising:
a) providing the base silicon wafer having front and back sides, wherein the front side comprises integrated circuits disposed thereon and wherein the base silicon wafer comprises at least one conductive via comprising conductive metal;
b) affixing the front side of the base silicon wafer having integrated circuits thereon to a carrier;
c) contacting the back side of the base silicon wafer with a polishing pad and a CMP slurry, said CMP slurry comprising:
1) a liquid carrier;
2) hydrogen peroxide at a level of 0.02 weight percent to less than 0.50 weight percent;
3) an abrasive; and
4) at least one chelating agent selected from the group consisting of glycine, alanine, asparagine, aspartic acid, cysteine, glutamic acid, glutamine, proline, serine, tyrosine, arginine, histidine ethylenediamine tetraacetic acid, alkane amine: and
d) polishing the backside of the base silicon wafer until at least one conductive via is exposed or further exposed, wherein silicon on the base silicon wafer is polished using the CMP slurry at a removal rate of at least 5,000 angstroms per minute at 6 psi or less of down-force; and ratio of removal rates of the silicon and the conductive metal ranging from 2:1 to 0.5:1.
2. The method of claim 1 wherein the conductive metal is selected from the group consisting of copper and tungsten.
3. The method of claim 2 wherein the conductive metal is copper.
4. The method of claim 3 wherein the copper:silicon selectivity ranges from 1.5:1 to 0.67:1.
5. The method of claim 3 wherein the copper:silicon selectivity ranges from 1.2:1 to 0.8:1.
6. The method of claim 1 wherein the liquid carrier comprises water.
7. The method of claim 1 wherein the backside of the base silicon wafer is not subjected to a grinding step before chemically mechanically polishing the backside of the base silicon wafer.
8. The method of claim 1 wherein the backside of the base silicon wafer is subjected to a grinding step before chemically mechanically polishing the backside of the base silicon wafer.
9. The method of claim 1 wherein the hydrogen peroxide level is in the range of 0.1 to 0.25 weight percent.
10. The method of claim 1 wherein the hydrogen peroxide level is in the range of 0.15 to 0.2 weight percent.
11. The method of claim 1 , wherein the at least one metal chelating agent is glycine.
12. A method for preparing a base silicon wafer for constructing an assembly comprising at least two integrated circuit chips at least one of which is from the base silicon wafer, said method comprising:
a) providing the base silicon wafer having front and back sides, wherein the front side comprises integrated circuits disposed thereon and wherein the base wafer comprises at least one conductive via comprising conductive metal;
b) affixing the front side of the base silicon wafer having integrated circuits thereon to a carrier;
c) contacting the back side of the base silicon wafer with a polishing pad and a CMP slurry, said CMP slurry comprising:
1) a liquid carrier;
2) hydrogen peroxide at a level of 0.02 weight percent to less than 0.50 weight percent;
3) an abrasive which may be suspended in the slurry, which may be affixed to a polishing pad, or both; and
4) at least one metal chelating agent selected from the group consisting of glycine, alanine, asparagine, aspartic acid, cysteine, glutamic acid, glutamine, proline, serine, tyrosine, arginine, histidine ethylenediamine tetraacetic acid, alkane amine; and
d) polishing the backside of the base silicon wafer until at least one conductive via is exposed or further exposed, wherein the base silicon wafer is polished using the CMP slurry at a rate of at least 5,000 angstroms per minute at 6 psi or less of down-force ; and ratio of removal rates of the silicon and the conductive metal ranging from 2:1 to 0.5:1.
13. The method of claim 12 , wherein the at least one metal chelating agent is glycine.