IP Library Granted Patent US 8,553,126
Granted Patent B2
US 8,553,126 · App. 12/967,299 · Granted Oct 8, 2013

Image sensor with charge multiplication

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Quick Facts
Patent No.
US 8,553,126
App. No.
12/967,299
Granted
Oct 8, 2013
Kind
B2
Abstract

An image sensor includes a horizontal shift register electrically connected to a pixel array for receiving charge packets from the pixel array. A non-destructive sense node is connected to an output of the horizontal shift register. A charge directing switch is electrically connected to the non-destructive sense node. The charge directing switch includes two outputs. A charge multiplying horizontal shift register is electrically connected to one output of the charge directing switch. A bypass horizontal shift register or an amplifier can be connected to the other output of the charge directing switch.

Claims (36)

1. An image sensor, comprising:

a horizontal shift register electrically connected to a pixel array for receiving charge packets directly from the pixel array;

a non-destructive sense node connected to an output of the horizontal shift register;

a charge sensing output channel electrically connected to the non-destructive sense node and configured to output a signal corresponding to a size of each charge packet received at the non-destructive sense node;

a charge directing switch electrically connected to the non-destructive sense node, the charge directing switch (i) comprising first and second outputs and (ii) being configured to direct charge packets, on a pixel-by-pixel basis, to the first output or the second output in response to the signal output by the charge sensing output channel;

a charge multiplying horizontal shift register electrically connected to the first output of the charge directing switch; and

a first amplifier electrically connected to the second output of the charge directing switch.

2. The image sensor as in claim 1 , wherein the charge sensing output channel comprises a second amplifier.

3. The image sensor as in claim 1 , further comprising a pipeline delay horizontal shift register connected between the non-destructive sense node and the charge directing switch.

4. The image sensor as in claim 1 , further comprising an extended horizontal shift register connected between the first output of the charge directing switch and an input of the charge multiplying horizontal shift register.

5. The image sensor as in claim 1 , further comprising a third amplifier connected to an output of the charge multiplying horizontal shift register.

6. An image capture device comprising:

an image sensor, comprising:

a horizontal shift register electrically connected to a pixel array for receiving charge packets from the pixel array;

a non-destructive sense node connected to an output of the horizontal shift register;

a charge sensing output channel electrically connected to the non-destructive sense node and configured to output a signal corresponding to a size of each charge packet received at the non-destructive sense node;

a charge directing switch electrically connected to the non-destructive sense node, the charge directing switch (i) comprising first and second outputs and (ii) being configured to direct charge packets, on a pixel-by-pixel basis, to the first output or the second output in response to the signal output by the charge sensing output channel;

a charge multiplying horizontal shift register electrically connected to the first output of the charge directing switch; and

a first amplifier electrically connected to the second output of the charge directing switch; and

a computing device (i) electrically connected to the charge directing switch and (ii) adapted to transmit the signal output by the charge sensing output channel to the charge directing switch.

7. The image capture device as in claim 6 , further comprising:

a second amplifier disposed within the charge sensing output channel; and

a third amplifier connected to an output of the charge multiplying horizontal shift register.

8. The image capture device as in claim 7 , further comprising:

a first output circuit connected to an output of the first amplifier;

a second output circuit connected to an output of the second amplifier;

a third output circuit connected to an output of the third amplifier,

wherein the first, second, and third output circuits each include an analog-to-digital converter electrically connected to the outputs of the first, second, and third amplifiers, respectively.

9. The image capture device as in claim 8 , further comprising a pipeline delay horizontal shift register connected between the non-destructive sense node and the charge directing switch.

10. The image capture device as in claim 9 , wherein a length of the pipeline delay horizontal shift register is based on a pipeline delay time of the second amplifier and the second output circuit.

11. The image capture device as in claim 6 , further comprising an extended horizontal shift register connected between the first output of the charge directing switch and an input of the charge multiplying horizontal shift register.

12. The image sensor as in claim 1 , further comprising a non-charge-multiplying bypass horizontal shift register electrically connected between the second output of the charge directing switch and the first amplifier.

13. The image sensor as in claim 12 , wherein a length of the non-charge-multiplying bypass horizontal shift register and a length of the charge multiplying horizontal shift register are substantially equal.

14. The image sensor as in claim 3 , wherein a length of the pipeline delay horizontal shift register corresponds to a pipeline processing delay of the charge sensing output channel.

15. The image capture device as in claim 6 , further comprising a non-charge-multiplying bypass horizontal shift register electrically connected between the second output of the charge directing switch and the first amplifier.

16. The image capture device as in claim 15 , wherein a length of the non-charge-multiplying bypass horizontal shift register and a length of the charge multiplying horizontal shift register are substantially equal.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
RELEASE OF SECURITY INTEREST Recorded Sep 22, 2015
From: TRUESENSE IMAGING, INC
To: PNC BANK, NATIONAL ASSOCIATION
Reel/Frame 036656/0412 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2014
From: TRUESENSE IMAGING, INC.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 033460/0457 →
TERMINATION AND RELEASE OF PATENT SECURITY AGREEMENT Recorded May 19, 2014
From: PNC BANK, NATIONAL ASSOCIATION
To: TRUESENSE IMAGING, INC.
Reel/Frame 032936/0167 →