IP Library Granted Patent US 8,479,374
Granted Patent B2
US 8,479,374 · App. 12/967,341 · Granted Jul 9, 2013

Method of producing an image sensor having multiple output channels

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Quick Facts
Patent No.
US 8,479,374
App. No.
12/967,341
Granted
Jul 9, 2013
Kind
B2
Abstract

A method for producing an image sensor includes providing a horizontal shift register electrically connected to a pixel array for receiving charge packets from the pixel array. A non-destructive sense node is provided that is connected to an output of the horizontal shift register. A charge directing switch is provided that is electrically connected to the non-destructive sense node. The charge directing switch includes first and second outputs. A charge multiplying horizontal shift register is provided that is electrically connected to the first output of the charge directing switch. A bypass horizontal shift register or an amplifier is provided that is connected to the second output of the charge directing switch.

Claims (20)

1. A method for producing an image capture device comprising:

providing a horizontal shift register electrically connected to a pixel array for receiving charge packets from the pixel array;

providing a non-destructive sense node connected to an output of the horizontal shift register;

providing a charge directing switch electrically connected to the non-destructive sense node, the charge directing switch being configured to receive charge from the non-destructive sense node and supply the received charge either to a first output or a second outputs;

providing a charge multiplying horizontal shift register electrically connected to the first output of the charge directing switch;

providing a first amplifier electrically connected to an output of the charge multiplying horizontal shift register, the first amplifier being configured to receive charge from the charge multiplying horizontal shift register and output a voltage signal corresponding to an amount of the charge received from the charge multiplying horizontal shift register; and

providing a second amplifier, different from the first amplifier, electrically connected to the second output of the charge directing switch, the second amplifier being configured to receive charge from the charge directing switch and output a voltage signal corresponding to an amount of the charge received from the charge directing switch.

2. The method as in claim 1 , further comprising:

providing a third amplifier connected to the non-destructive sense node, the third amplifier being configured to receive, from the non-destructive sense node, a voltage corresponding to an amount of charge sensed by the non-destructive sense node.

3. The method as in claim 1 , further comprising:

providing a first output circuit connected to an output of the first amplifier, the first output circuit comprising a first analog-to-digital converter electrically connected to the output of the first amplifier; and

providing a second output circuit connected to an output of the second amplifier, the second output circuit comprising a second analog-to-digital converter electrically connected to the output of the second amplifier.

4. The method as in claim 1 , further comprising:

providing a bypass horizontal shift register connected between the second output of the charge directing switch and the second amplifier.

5. The method as in claim 4 , wherein a length of the bypass horizontal shift register and a length of the charge multiplying horizontal shift register are substantially equal.

6. The method as in claim 3 , further comprising providing a pipeline delay horizontal shift register connected between the non-destructive sense node and the charge directing switch.

7. The method as in claim 6 , further comprising providing a third output circuit connected to an output of the third amplifier, the third output circuit comprising a third analog-to-digital converter electrically connected to the output of the third amplifier, wherein a length of the pipeline delay horizontal shift register is based on a pipeline delay time of the third amplifier and the third output circuit.

8. The method as in claim 1 , further comprising providing an extended horizontal shift register connected between the first output of the charge directing switch and an input of the charge multiplying horizontal shift register.

9. The method as in claim 1 , further comprising providing a computing device electrically connected to the charge directing switch, wherein (i) the computing device is adapted to transmit a switch signal to the charge directing switch in response to a signal received from the non-destructive sense node, (i) the signal from the non-destructive sense node corresponds to an amount of charge sensed by the non-destructive sense node, and (iii) the switch signal directs the charge directing switch to supply charge received from the non-destructive sense node to either the first or second output based on the amount of charge sensed by the non-destructive sense node.

10. The method as in claim 2 , wherein the charge directing switch is configured to direct received charge, on a pixel-by-pixel basis, to the first output or the second output in response to a voltage signal output by the third amplifier.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
RELEASE OF SECURITY INTEREST Recorded Sep 22, 2015
From: TRUESENSE IMAGING, INC
To: PNC BANK, NATIONAL ASSOCIATION
Reel/Frame 036656/0412 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2014
From: TRUESENSE IMAGING, INC.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 033460/0457 →
TERMINATION AND RELEASE OF PATENT SECURITY AGREEMENT Recorded May 19, 2014
From: PNC BANK, NATIONAL ASSOCIATION
To: TRUESENSE IMAGING, INC.
Reel/Frame 032936/0167 →