IP Library Granted Patent US 8,289,082
Granted Patent B2
US 8,289,082 · App. 12/977,034 · Granted Oct 16, 2012

Circuit and method for adjusting an offset output current for an input current amplifier

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Quick Facts
Patent No.
US 8,289,082
App. No.
12/977,034
Granted
Oct 16, 2012
Kind
B2
Abstract

A circuit and a method for correcting an offset is provided that includes a current amplifier and an adjusting circuit for correcting an offset of an output current of the current amplifier. Wherein the adjusting circuit has a controlled current source, an output of the controlled current source is connected to the current amplifier for impressing an output current of the controlled current source in the current amplifier, an input of the controlled current source to form a regulation element of a control loop is connected by a first switching device of the adjusting circuit to an output of the current amplifier and to form a holding element is disconnected from the output of the current amplifier by the first switching device. The controlled current source, acting as a regulation element in the control loop, is set up to regulate the offset to a minimum by setting of a current value of the output current, and the controlled current source, acting as a holding element, is set up to hold the current value, associated with the minimum, of the output current.

Claims (50)

1. A circuit comprising:

a current amplifier; and

an adjusting circuit configured to correct an offset of an output current of the current amplifier, the adjusting circuit having a controlled current source and a first switching device,

wherein an output of the controlled current source is connectable to the current amplifier for producing an output current of the controlled current source in the current amplifier,

wherein an input of the controlled current source is connectable by the first switching device of the adjusting circuit to an output of the current amplifier to form a regulation element of a control loop,

wherein the input of the controlled current source is disconnected from the output of the current amplifier by the first switching device to form a holding element,

wherein the controlled current source, acting as a regulation element in the control loop, is configured to regulate the offset to a minimum by setting a current value of the output current, and

wherein the controlled current source, acting as a holding element, is configured to hold the current value, associated with the minimum, of the output current.

2. The circuit according to claim 1 , wherein the controlled current source has a capacitor.

3. The circuit according to claim 1 , wherein the controlled current source is controllable by a control voltage.

4. The circuit according to claim 1 , wherein the controlled current source has a transistor, which by means of a control voltage at a control input of the transistor controls the output current of the controlled current source.

5. The circuit according to claim 1 , wherein the controlled current source has a storage device or a capacitor for storing a control voltage.

6. The circuit according to claim 5 , wherein the controlled current source has the capacitor and the capacitor of the controlled current source, which acts as a regulation element, is connectable to the output of the current amplifier by the first switching device for charging the capacitor until a steady state is attained for a minimum offset.

7. The circuit according to claim 1 , wherein the current amplifier has a first current mirror and a second current mirror for current amplification, whose outputs are connected to the output of the current amplifier.

8. The circuit according to claim 1 , wherein the adjusting circuit has a constant current source, which is connected to the current amplifier for producing a constant current.

9. The circuit according to claim 8 , wherein the current amplifier has a current summing node that is connectable to the output of the current amplifier, wherein at least one first current and one second current are summed in the current summing node, wherein the first current is the output current of the controlled current source or is based on the output current of the controlled current source, and wherein the second current is the constant current of the constant current source or is based on the constant current of the constant current source.

10. The circuit according to claim 9 , wherein the first current or the second current enters the summation with a negative sign.

11. The circuit according to claim 1 , wherein the adjusting circuit has a second switching device that is connectable via an input of the adjusting circuit to the output of the current amplifier and to the circuit output.

12. The circuit according to claim 1 , wherein the adjusting circuit has a second switching device, which is connectable to a capacitor and is configured to discharge the capacitor in a closed state.

13. The circuit according to claim 1 , further comprising a control circuit that is configured to control the first switching device and is connectable to a control terminal of the first switching device.

14. The circuit according to claim 11 , further comprising a control circuit that is connectable to a control terminal of the second switching device to control the second switching device.

15. The circuit according to claim 12 , further comprising a control circuit that is connectable to a control terminal of the second switching device to control the second switching device.

16. The circuit according to claim 1 , further comprising a control circuit that is configured:

in a first step, to disconnect the output of the current amplifier from the circuit output by opening of a second switching device,

in a second step, to connect a capacitor of the controlled current source to the output of the current amplifier by closing the first switching device, after the second step a capacitor is charged by a charging current and by the charging of the capacitor an output current of the controlled current source is increased until the charging current attains a minimum,

in a third step, to disconnect the charged capacitor of the controlled current source from the output of the current amplifier by opening the first switching device, and

in a fourth step, to connect the output of the current amplifier to the circuit output by closing the second switching device.

17. A method for correcting an offset of an output current of a current amplifier of a circuit, the method comprising:

connecting a controlled current source to an output of the current amplifier via a first switching device, to form a regulation element of a control loop;

regulating an offset to a minimum by setting a current value of the output current of the controlled current source when an input signal of the current amplifier has a constant value, the controlled current source acting as the regulation element; and

disconnecting the controlled current source from the output of the current amplifier by the first switching device to form a holding element for holding the current value associated with the minimum of the output current.

18. The method according to claim 17 , wherein the controlled current source has a capacitor.

19. The method according to claim 17 , wherein the controlled current source is controllable by a control voltage.

20. The method according to claim 17 , wherein the controlled current source has a transistor, which by means of a control voltage at a control input of the transistor controls the output current of the controlled current source.

21. The method according to claim 17 , wherein the controlled current source has a storage device or a capacitor for storing a control voltage.

22. The method according to claim 21 , wherein the controlled current source has the capacitor and the capacitor of the controlled current source, which acts as a regulation element, is connectable to the output of the current amplifier by the first switching device for charging the capacitor until a steady state is attained for a minimum offset.

23. The method according to claim 17 , wherein the current amplifier has a first current mirror and a second current mirror for current amplification, whose outputs are connected to the output of the current amplifier.

24. The method according to claim 17 , wherein an adjusting circuit has a constant current source, which is connected to the current amplifier for producing a constant current.

25. The method according to claim 24 , wherein the current amplifier has a current summing node that is connectable to the output of the current amplifier, wherein at least one first current and one second current are summed in the current summing node, wherein the first current is the output current of the controlled current source or is based on the output current of the controlled current source, and wherein the second current is the constant current of the constant current source or is based on the constant current of the constant current source.

26. The method according to claim 25 , wherein the first current or the second current enters the summation with a negative sign.

27. The method according to claim 17 , wherein an adjusting circuit has a second switching device that is connectable via an input of the adjusting circuit to the output of the current amplifier and to the circuit output.

28. The method according to claim 17 , wherein an adjusting circuit has a second switching device, which is connectable to a capacitor and is configured to discharge the capacitor in a closed state.

29. The method according to claim 17 , further comprising a control circuit that is configured to control the first switching device and is connectable to a control terminal of the first switching device.

30. The method according to claim 27 , further comprising a control circuit that is connectable to a control terminal of the second switching device to control the second switching device.

31. The method according to claim 28 , further comprising a control circuit that is connectable to a control terminal of the second switching device to control the second switching device.

32. The method according to claim 17 , further comprising:

disconnecting, by a control circuit in a first step, the output of the current amplifier from the circuit output by opening of a second switching device,

connecting, by the control circuit and in a second step, a capacitor of the controlled current source to the output of the current amplifier by closing the first switching device, after the second step a capacitor is charged by a charging current and by the charging of the capacitor an output current of the controlled current source is increased until the charging current attains a minimum,

disconnecting, by the control circuit and in a third step, the charged capacitor of the controlled current source from the output of the current amplifier by opening the first switching device, and

connecting, by the control circuit and in a fourth step, the output of the current amplifier to the circuit output by closing the second switching device.

Assignments (15)
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: ATMEL CORPORATION
Reel/Frame 059262/0105 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
NUNC PRO TUNC ASSIGNMENT Recorded Jul 8, 2020
From: SONRAI MEMORY LIMITED
To: ARIGNA TECHNOLOGY LIMITED
Reel/Frame 053147/0853 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2020
From: MICROCHIP TECHNOLOGY INC.; ATMEL CORPORATION; MICROSEMI CORPORATION
To: SONRAI MEMORY LIMITED
Reel/Frame 051799/0956 →
RELEASE OF SECURITY INTEREST Recorded Dec 21, 2019
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; ATMEL CORPORATION
Reel/Frame 051398/0809 →
RELEASE OF SECURITY INTEREST Recorded Dec 21, 2019
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; ATMEL CORPORATION
Reel/Frame 051398/0827 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: ATMEL CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041715/0747 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Apr 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: ATMEL CORPORATION
Reel/Frame 038376/0001 →
PATENT SECURITY AGREEMENT Recorded Jan 3, 2014
From: ATMEL CORPORATION
To: MORGAN STANLEY SENIOR FUNDING, INC. AS ADMINISTRATIVE AGENT
Reel/Frame 031912/0173 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 29, 2012
From: ATMEL AUTOMOTIVE GMBH
To: ATMEL CORPORATION
Reel/Frame 028470/0720 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME PREVIOUSLY RECORDED ON REEL 025536 FRAME 0853. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNEE'S NAME IS ATMEL AUTOMOTICE GMBH. Recorded Mar 1, 2011
From: PROHASKA, ARMIN; SAETHER, TERJE; VOGELMANN, HOLGER
To: ATMEL AUTOMOTIVE GMBH
Reel/Frame 025880/0560 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 22, 2010
From: PROHASKA, ARMIN; SAETHER, TERJE; VOGELMANN, HOLGER
To: ATEML AUTOMOTIVE GMBH
Reel/Frame 025536/0853 →