Circuit providing load isolation and memory domain translation for memory module
View Patent ↗A circuit is configured to be mounted on a memory module configured to be operationally coupled to a computer system. The memory module has a first number of ranks of double-data-rate (DDR) memory devices configured to be activated concurrently with one another in response to a first number of chip-select signals. The circuit is configurable to receive a set of signals comprising address signals and a second number of chip-select signals, the address signals comprising bank address signals. The circuit is further configurable to monitor command signals received by the memory module, to selectively isolate a load of at least one rank of the first number of ranks from the computer system in response to the command signals, and to provide the first number of chip-select signals to the first number of ranks in response at least in part to the received bank address signals and the received second number of chip-select signals.
1. A circuit configured to be mounted on a memory module configured to be operationally coupled to a computer system, the memory module having a first number of ranks, each rank of the first number of ranks comprising a plurality of double-data-rate (DDR) memory circuits that are configured to be activated concurrently with one another in response to a first number of chip-select signals, the first number of ranks comprising a first number of DDR memory circuits, the circuit configurable to:
receive a set of signals comprising address signals and a second number of chip-select signals, the address signals comprising bank address signals, wherein the received set of signals are capable of controlling a memory module having a second number of ranks, each rank of the second number of ranks comprising a second plurality of DDR memory circuits that are configured to be activated concurrently with one another, the second number of ranks comprising a second number of DDR memory circuits, the second number of ranks smaller than the first number of ranks, the second number of chip-select signals smaller than the first number of chip-select signals, and the second number of DDR memory circuits smaller than the first number of DDR memory circuits;
monitor command signals received by the memory module;
selectively isolate a load of at least one rank of the first number of ranks from the computer system in response to the command signals; and
provide the first number of chip-select signals to the first number of ranks in response at least in part to the received bank address signals and the received second number of chip-select signals.
2. The circuit of claim 1 , wherein the circuit is further configurable to store an address signal of the received set of signals during a row access procedure and to pass the stored address signal as an address signal to the first number of ranks during a subsequent column address procedure.
3. The circuit of claim 1 , wherein the circuit is further configurable to buffer a plurality of the received address signals during a row access procedure and to transmit the plurality of the received address signals to the first number of ranks during a subsequent column access procedure.
4. The circuit of claim 1 , wherein the circuit is further configurable to receive an input command signal from the computer system and to generate and transmit an output command signal to the first number of ranks.
5. The circuit of claim 4 , wherein the circuit is further configurable to respond at least in part to the received bank address signals and the received second number of chip-select signals by selecting at least one rank of the first number of ranks and transmitting the output command signal to the selected at least one rank of the first number of ranks.
6. The circuit of claim 1 , wherein the circuit is configurable to control isolation of data strobe signal lines in response to the command signals.
7. The circuit of claim 1 , wherein the circuit has a load and selectively isolating a load of the at least one rank from the computer system comprises presenting the load of the circuit to the computer system.
8. The circuit of claim 1 , wherein the circuit is further configurable to selectively electrically couple the first number of ranks to the computer system and to selectively isolate the first number of ranks from one another and from the computer system.
9. The circuit of claim 8 , wherein the circuit is further configurable to provide data paths for each rank of the first number of ranks, wherein the data paths are separate from one another.
10. The circuit of claim 8 , wherein the circuit is further configurable to provide data paths for each rank of the first number of ranks, wherein the data paths are separate from the computer system.
11. The circuit of claim 1 , wherein the circuit is further configurable to generate control signals in response to one or more control signals of the received set of signals and transmit the generated control signals to the first number of DDR memory circuits.
12. The circuit of claim 11 , wherein the one or more control signals comprises a row address bit and the circuit is further configurable to latch the row address bit.
13. The circuit of claim 1 , wherein the circuit is further configurable to transmit a set of output signals to the first number of ranks.
14. The circuit of claim 13 , wherein the circuit is further configurable to receive the command signals from the computer system, to select at least one rank of the first number of ranks, and to transmit the command signals to the selected at least one rank.
15. The circuit of claim 1 , wherein the circuit is further configurable to selectively isolate a data signal line of the first number of ranks from the computer system.
16. The circuit of claim 1 , wherein the memory module has attributes and the circuit is further configurable to store data accessible to the computer system, wherein the data characterizes the memory module as having attributes that are different from the attributes of the memory module.
17. The circuit of claim 16 , wherein the attributes are selected from a group consisting of: a number of row addresses, a number of column addresses, a number of DDR memory circuits, a data width of the DDR memory circuits, a memory density per DDR memory circuit, a number of ranks, and a memory density per rank.
18. A method of using a memory module configured to be operationally coupled to a computer system, the memory module having a first number of ranks, each rank of the first number of ranks comprising a plurality of double-data-rate (DDR) memory circuits that are configured to be activated concurrently with one another in response to a first number of chip-select signals, the first number of ranks comprising a first number of DDR memory circuits, the method comprising:
receiving a set of signals comprising address signals and a second number of chip-select signals, the address signals comprising bank address signals, wherein the received set of signals are capable of controlling a memory module with a second number of ranks, each rank of the second number of ranks comprising a second plurality of DDR memory circuits that are configured to be activated concurrently with one another, the second number of ranks comprising a second number of DDR memory circuits, the second number of ranks smaller than the first number of ranks, the second number of chip-select signals smaller than the first number of chip-select signals, and the second number of DDR memory circuits smaller than the first number of DDR memory circuits;
monitoring command signals received by the memory module;
selectively isolating a load of at least one rank of the first number of ranks from the computer system in response to the command signals; and
providing the first number of chip-select signals to the first number of ranks in response at least in part to the received bank address signals and the received second number of chip-select signals.
19. The method of claim 18 , further comprising buffering a plurality of the received address signals during a row access procedure and transmitting the plurality of the received address signals to the first number of ranks during a subsequent column access procedure.
20. The method of claim 18 , further comprising receiving an input command signal from the computer system and providing an output command signal to the first number of ranks.
21. The method of claim 20 , further comprising responding at least in part to the received bank address signals and the received second number of chip-select signals by selecting at least one rank of the first number of ranks and transmitting the output command signal to the selected at least one rank of the first number of ranks.
22. The method of claim 18 , wherein selectively isolating a load of the at least one rank from the computer system comprises presenting a smaller load to the computer system.
23. The method of claim 18 , further comprising selectively isolating a data signal line of the first number of ranks from the computer system.
24. The method of claim 18 , wherein the memory module has attributes and the method further comprises storing data accessible to the computer system, wherein the data characterizes the memory module as having attributes that are different from the attributes of the memory module.
25. The method of claim 24 , wherein the attributes are selected from a group consisting of: a number of row addresses, a number of column addresses, a number of DDR memory circuits, a data width of the DDR memory circuits, a memory density per DDR memory circuit, a number of ranks, and a memory density per rank.