Implementing semiconductor SoC with metal via gate node high performance stacked transistors

1. A method for implementing stacked vertical transistors in a back-end-of-line (BEOL) structure on a semiconductor System on Chip (SoC) comprising: forming a pair of stacked vertical field effect transistors (FETs) by polycrystalline depositions in a stack between planes of a respective global signal routing wire in the back-end-of-line (BEOL) structure; said polycrystalline depositions of each of said pair of stacked vertical FETs including sequential source deposition, channel deposition and drain deposition; and forming a wire via defining a gate node of each of said pair of stacked vertical FETs by forming an etched hole through said source deposition, channel deposition and drain deposition, and an ohmic contact, and a dielectric layer to a signal wire in the BEOL stack; depositing a thin dielectric in said etched opening, and removing said thin dielectric from a bottom of said etched opening, and depositing a metal in said etched opening.

2. The method as recited in claim 1 wherein said pair of stacked vertical field effect transistors (FETs) includes a stacked N-channel field effect transistor (NFET) and a P-channel field effect transistor (PFET).

3. The method as recited in claim 2 wherein said polycrystalline depositions of each of said pair of stacked vertical FETs include a sequential deposition of an N+ doped polysilicon defining a N source, a P− doped polysilicon defining a N body, and an N+ doped polysilicon defining a N drain, depositing an ohmic contact on said NFET N+ doped polysilicon drain deposition; and a sequential deposition of a P+ doped polysilicon defining a P source, an N− doped polysilicon defining a P body, and a P+ doped polysilicon defining a P drain.

4. The method as recited in claim 2 includes forming a wire via for defining an output via connected to a common connection of a series connected pair of said NFET and said PFET.

5. The method as recited in claim 3 wherein sequential source deposition, channel deposition and drain deposition of said NFET and said PFET has a respective thickness of approximately 0.1 μm, 0.05 μm, and 0.1 μm.

6. A method for implementing stacked vertical transistors in a back-end-of-line (BEOL) structure comprising:

forming a pair of stacked vertical field effect transistors (FETs) being formed by polycrystalline depositions in a stack between planes of a respective global signal routing wire; said polycrystalline depositions of each of said pair of stacked vertical FETs including a sequential deposition of an N+ doped polysilicon defining a N source, a P− doped polysilicon defining a N body, and an N+ doped polysilicon defining a N drain, depositing an ohmic contact on said NFET N+ doped polysilicon drain deposition; and a sequential deposition of a P+ doped polysilicon defining a P source, an N− doped polysilicon defining a P body, and a P+ doped polysilicon defining a P drain

said polycrystalline depositions of each of said pair of stacked vertical FETs including sequential source deposition, channel deposition and drain deposition; and

forming a wire via defining a gate node of each of said pair of stacked vertical FETs includes forming an etched hole through said source deposition, channel deposition and drain deposition of said NFET and said PFET, and said ohmic contact, and a dielectric layer to a signal wire in the BEOL stack; depositing a thin dielectric in said etched opening, and removing said thin dielectric from a bottom of said etched opening, and depositing a metal in said etched opening.