Semiconductor flip chip package having substantially non-collapsible spacer and method of manufacture thereof
View Patent ↗A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has a spacer to maintain a separation between the die and the die paddle. Also, methods for making the package are disclosed.
1. A flip chip package having, in addition to electrical flip chip interconnects, a substantially non-collapsible spacer on a tie bar, the spacer electrically insulated from a die and between an active side of the die and a surface of the tie bar.
2. The package of claim 1 , the spacer having a base at the support surface and a summit at the die active surface.
3. The package of claim 2 wherein the base is wider than the summit.
4. The package of claim 1 wherein the spacer is generally conical.
5. The package of claim 1 wherein the spacer has a shape generally as a truncated sphere in contact with the surface.
6. The package of claim 2 wherein a width of the base is less than about twice a width of the interconnects.
7. The package of claim 6 wherein the width of the base is less than about the width of the base of the interconnects.
8. The package of claim 1 wherein the flip chip interconnects are of a material of a low melt solder.
9. The package of claim 1 wherein the flip chip interconnects are of a material of a eutectic solder.
10. The package of claim 1 wherein a material of the spacer comprises a metal.
11. The package of claim 10 wherein the material of the spacer comprises gold.
12. The package of claim 10 wherein the material of the spacer comprises a gold stud bump structure.
13. The package of claim 1 wherein a material of the spacer comprises a polymer.
14. The package of claim 1 wherein a material of the spacer comprises an epoxy.
15. A flip chip package comprising:
a substrate, including a lead and a die mounted in a flip chip arrangement on a surface of the substrate;
a flip chip interconnection between an active side of the die and a bond site on another lead; and
a non-collapsible spacer on the lead, the spacer between the lead and the die, the spacer electrically insulated from the die.
16. The package of claim 15 , further comprising at least another of the spacer between the substrate and the die.
17. The package of claim 15 , further comprising at least two of another of the spacer between the substrate and the die.
18. The package of claim 15 , further comprising at least three of another of the spacer between the substrate and the die.
19. The package of claim 15 wherein the spacer is situated near a periphery of a footprint of the die.
20. The package of claim 15 wherein the spacer is situated in an area near a center of a footprint of the die.
21. A method for making a flip chip package comprising:
providing at least one non-collapsible spacer on a surface of a lead;
providing a die having fusible metal interconnects attached thereon with a height of the interconnects greater than a height of the non-collapsible spacer on the lead and electrically insulated from the die;
contacting the interconnects with bond sites on the lead; and
melting the fusible metal so that the fusible metal interconnects collapse, the die contacts the spacer, and allowing the fusible metal to harden.