Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation
View Patent ↗A multilayer wiring structure of a semiconductor device having a stacked structure is arranged to restrain reliability degradation due to stress applied to the region of wiring between opposite upper and lower plugs. The rate of overlap of contact surface between upper plug and wiring on contact surface between lower plug and wiring, is small to the extent that no void is generated. The multilayer wiring structure is produced such that no grain boundary is contained in the region of wiring between upper and lower plugs. The difference in thermal expansion coefficient between the material of wiring and the material of upper and lower plugs, is small to the extent that no void is generated.
1. A method of producing a wiring structure of a semiconductor device, comprising:
a step (a) of forming a first opening in a first insulating layer formed above a substrate and forming a lower plug in the first opening;
a step (b) of forming a wiring layer above the first insulating layer and the lower plug;
a step (c) of forming a second insulating layer above the wiring layer, and forming, in the second insulating layer, a second opening opposite to the first opening, and forming an upper plug in the second opening;
wherein by heat treatment at the step (b), in a case that there is a single grain in a first region of the wiring layer between the upper plug and the lower plug, a size of the grain in the first region becomes substantially equal to a size of a single grain or an average size of grains in a second region of the wiring layer not between the upper plug and the lower plug and, in case that there are a number of grains in the first region, average size of the grains in the first region becomes substantially equal to the size of the single grain or the average size of the grains in the second region.
2. The method according to claim 1 wherein the second region of the wiring layer is between the first insulating layer and the second insulating layer.
3. The method according to claim 1 , wherein the second region of the wiring layer is between a different upper plug from the upper plug and a different lower plug from the lower plug.
4. The method according to claim 1 , wherein the wiring layer has a layer including aluminium or aluminium alloy.
5. The method according to claim 1 , wherein at the step (b), the wiring layer is formed by sputtering, at a deposition temperature of about 200° C. or more.