Electrode configurations for semiconductor devices

1. A method of forming a III-N device, comprising:

forming an electrode-defining layer having a thickness on a surface of a III-N material structure that has a 2DEG formed therein;

patterning a masking layer over the electrode-defining layer, the masking layer including an opening having a width;

performing an etching step, the etching step comprising etching the electrode-defining layer beneath the opening to form a recess therein, the recess having a sidewall which comprises a plurality of steps, a portion of the recess distal from the III-N material structure having a first width, and a portion of the recess proximal to the III-N material structure having a second width, the first width being larger than the second width;

removing the masking layer; and

forming an electrode in the recess, the electrode including an extending portion over the sidewall, a portion of the electrode-defining layer being between the extending portion and the III-N material structure; wherein

the etching step includes a first procedure and a second procedure, the first procedure comprising removing a portion of the electrode-defining layer, and the second procedure comprising removing a portion of the masking layer without entirely removing the masking layer and without substantially etching the electrode-defining layer, the second procedure causing an increase in the width of the opening in the masking layer,

wherein the masking layer comprises photoresist; wherein the method further comprises redistributing the photoresist in the masking layer prior to performing the etching step; and wherein redistributing the photoresist causes the masking layer to have slanted sidewalls adjacent to the opening.

2. The method of claim 1 , wherein the first procedure is performed a second time after the second procedure has been performed.

3. The method of claim 2 , wherein the second procedure is performed a second time after the first procedure has been performed a second time.

4. The method of claim 1 , wherein redistributing the photoresist comprises thermally annealing the photoresist.

5. The method of claim 1 , wherein the etching step results in the recess extending through the entire thickness of the electrode-defining layer.

6. The method of claim 5 , wherein the etching step is a first etching step, the method further comprising performing a second etching step resulting in the recess further extending into the III-N material structure.

7. The method of claim 1 , further comprising forming an additional dielectric layer having a thickness between the electrode-defining layer and the III-N material structure.

8. The method of claim 7 , wherein the etching step results in the recess further extending through the entire thickness of the additional dielectric layer.

9. The method of claim 7 , wherein the device further comprises a passivation layer having a thickness between the electrode-defining layer and the additional dielectric layer.

10. The method of claim 9 , wherein the etching step results in the recess further extending through the entire thickness of the passivation layer.

11. The method of claim 1 , wherein the electrode is an anode and the III-N device is a diode.

12. The method of claim 1 , wherein the electrode is a gate, and the III-N device is a transistor.

13. The method of claim 1 , wherein the etching step results in the sidewall forming an effective angle of about 40 degrees or less relative to the surface of the III-N material structure.

14. The method of claim 1 , wherein the etching step results in at least one of the steps in the sidewall having a first surface that is substantially parallel to the surface of the III-N material structure and a second surface that is slanted, the second surface forming an angle of between 5 and 85 degrees with the surface of the III-N material structure.

15. A method of forming a semiconductor device, comprising:

forming an electrode-defining layer having a thickness on a surface of a III-N semiconductor material structure that has a 2DEG formed therein;

patterning a photoresist layer over the electrode-defining layer, the photoresist layer including an opening having a width;

performing a first etch, the first etch comprising etching the electrode-defining layer beneath the opening to form a recess therein, the recess having a sidewall;

after etching the electrode-defining layer, performing a second etch which removes a portion of the masking layer without entirely removing the masking layer, the second etch increasing the width of the opening in the masking layer;

after performing the second etch, performing a third etch which etches more of the electrode-defining layer beneath the opening and extends the recess;

removing the photoresist layer; and

forming an electrode in the recess,

wherein the method further comprises redistributing the photoresist in the photoresist layer prior to performing the first etch; wherein redistributing the photoresist causes the masking layer to have slanted sidewalls adjacent to the opening.

16. The method of claim 15 , wherein redistributing the photoresist comprises thermally annealing the photoresist.

17. The method of claim 15 , wherein the first etch or the third etch results in the sidewall of the recess being a slanted sidewall.

18. The method of claim 15 , wherein the second etch is a substantially isotropic etch.

19. The method of claim 15 , wherein the second etch removes the portion of the masking layer without substantially etching the electrode-defining layer.