Clock driver for a capacitance clock input
View Patent ↗A circuit that produces a clocking signal for a low to medium capacitance input of a device includes a drive gate connected to a common-base bi-polar driver circuit. The output of the drive gate is connected to an emitter of an NPN bi-polar transistor through one coupling capacitor and to an emitter of a PNP bi-polar transistor through another coupling capacitor. The transistors are connected in a common-base configuration with the collectors of the transistors connected together. One voltage is connected to the base of the PNP transistor. Another voltage is connected to the base of the NPN transistor. A diode is connected in parallel with the base-emitter of the PNP transistor. Another diode is connected in parallel with the base-emitter of the NPN transistor. A damping resistor is connected between the collectors of the transistors and the low to medium capacitance clock input of the device.
1. A circuit for producing a clocking signal for a capacitance clock input of a device, the circuit comprising:
an output of a drive gate connected to an emitter of an NPN bi-polar transistor through a first coupling capacitor and connected to an emitter of a PNP bi-polar transistor through a second coupling capacitor, wherein the NPN bi-polar transistor and the PNP bi-polar transistor are connected in a common base configuration with collectors of the NPN and PNP bi-polar transistors connected together;
a first DC voltage supply connected to a base of the PNP bi-polar transistor;
a second DC voltage supply connected to a base of the NPN bi-polar transistor, wherein a signal produced by the first DC voltage supply is larger than a signal produced by the second DC voltage supply;
a first diode connected in parallel with the base emitter of the PNP bi-polar transistor with an anode of the diode connected to the base of the PNP bi-polar transistor;
a second diode connected in parallel with the base emitter of the NPN bi-polar transistor with a cathode of the diode connected to the base of the NPN bi-polar transistor; and
a damping resistor connected between the collectors of the NPN and PNP bi-polar transistors and the capacitance clock input of the device.
2. The circuit of claim 1 , wherein the capacitance clock input comprises a last shift element of a horizontal shift register.
3. The circuit of claim 1 , wherein the capacitance clock input comprises a gate of a reset transistor.
4. A circuit for producing a clocking signal for a capacitance clock input of a device, the circuit comprising:
an output of a drive gate connected to an emitter of an NPN bi-polar transistor through a first coupling capacitor and connected to an emitter of a PNP bi-polar transistor through a second coupling capacitor, wherein the NPN bi-polar transistor and the PNP bi-polar transistor are connected in a common base configuration with collectors of the NPN and PNP bi-polar transistors connected together;
a first reference generator connected to a base of the PNP bi-polar transistor;
a second reference generator connected to a base of the NPN bi-polar transistor, wherein a signal produced by the first reference generator is larger than a signal produced by the second reference generator;
a first diode connected in parallel with the base emitter of the PNP bi-polar transistor with an anode of the diode connected to the base of the PNP bi-polar transistor;
a second diode connected in parallel with the base emitter of the NPN bi-polar transistor with a cathode of the diode connected to the base of the NPN bi-polar transistor; and
a damping resistor connected between the collectors of the NPN and PNP bi-polar transistors and the capacitance clock input of the device.
5. The circuit of claim 4 , wherein (i) the first reference generator is configured to compensate for a temperature-dependent base-emitter voltage of the PNP bi-polar transistor and (ii) the second reference generator is configured to compensate for a temperature-dependent base-emitter voltage of the NPN bi-polar transistor.