Bottom electrodes for use with metal oxide resistivity switching layers
View Patent ↗In a first aspect, a metal-insulator-metal (MIM) stack is provided that includes (1) a first conductive layer comprising a silicon-germanium (SiGe) alloy; (2) a resistivity-switching layer comprising a metal oxide layer formed above the first conductive layer; and (3) a second conductive layer formed above the resistivity-switching layer. A memory cell may be formed from the MIM stack. Numerous other aspects are provided.
1. A device comprising:
a metal-insulator-metal (MIM) stack comprising:
a first conductive layer comprising a silicon-germanium (SiGe) alloy;
a resistivity-switching layer comprising a metal oxide layer formed above the first conductive layer; and
a second conductive layer formed above the resistivity-switching layer; and
a diode coupled to and disposed above or below the MIM stack.
2. The device of claim 1 wherein the SiGe alloy comprises between about 5 and 35 atm % Ge.
3. The device of claim 1 wherein the first conductive layer has a thickness of about 2-100 nanometers.
4. The device of claim 1 wherein the metal oxide layer comprises one or more of HfO X , ZrO X , NiO X , TiO X , TaO X , NbO X or Al X O Y .
5. The device of claim 1 wherein the second conductive layer comprises titanium nitride.
6. The device of claim 5 wherein the second conductive layer comprises a layer stack having at least one of a titanium layer and a titanium oxide layer formed over the resistivity-switching layer and a titanium nitride layer formed thereover.
7. A memory cell comprising:
the device of claim 1 .
8. The memory cell of claim 7 wherein the diode comprises a vertical polysilicon diode coupled in series with the MIM stack.
9. The memory cell of claim 7 wherein the SiGe alloy comprises between about 5 and 35 atm % Ge.
10. The memory cell of claim 7 wherein the first conductive layer has a thickness of about 2-100 nanometers.
11. The memory cell of claim 7 wherein the metal oxide layer comprises one or more of HfO X , ZrO X , NiO X , TiO X , TaO X , NbO X or Al X O Y .
12. The memory cell of claim 7 wherein the second conductive layer comprises a layer stack having at least one of a titanium layer and a titanium oxide layer formed over the resistivity-switching layer and a titanium nitride layer formed thereover.
13. A method of forming a device, the method comprising:
forming a metal-insulator-metal (MIM) stack comprising:
forming a first conductive layer comprising a silicon-germanium (SiGe) alloy;
forming a resistivity-switching layer comprising a metal oxide layer above the first conductive layer; and
forming a second conductive layer above the resistivity-switching layer; and
forming a diode coupled to and disposed above or below the MIM stack.
14. The method of claim 13 wherein the first conductive layer is formed at a temperature of not more than about 600° C.
15. The method of claim 13 wherein the first conductive layer is formed at a temperature of not more than about 550° C.
16. The method of claim 13 wherein the first conductive layer is formed using low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition.
17. The method of claim 13 wherein the SiGe alloy comprises between about 5 and 35 atm % Ge.
18. The method of claim 13 wherein the second conductive layer comprises a layer stack having at least one of a titanium layer and a titanium oxide layer formed over the resistivity-switching layer and a titanium nitride layer formed thereover.
19. The method of claim 13 wherein the metal oxide layer comprises one or more of HfO X , ZrO X , NiO X , TiO X , TaO X , NbO X or Al X O Y .
20. A method of forming a memory cell comprising:
forming a metal-insulator-metal (MIM) stack having:
a first conductive layer comprising a silicon-germanium (SiGe) alloy;
a resistivity-switching layer comprising a metal oxide layer formed above the first conductive layer; and
a second conductive layer formed above the resistivity-switching layer; and
forming a steering element coupled to and disposed above or below the MIM stack.
21. The method of claim 20 wherein the first conductive layer is formed at a temperature of not more than about 600° C.
22. The method of claim 20 wherein the first conductive layer is formed at a temperature of not more than about 550° C.
23. The method of claim 20 wherein the first conductive layer is formed using low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition.
24. The method of claim 20 wherein the SiGe alloy comprises between about 5 and 35 atm % Ge.
25. The method of claim 20 wherein the metal oxide layer comprises one or more of HfO X , ZrO X , NiO X , TiO X , TaO X , NbO X or Al X O Y .