Forming borderless contact for transistors in a replacement metal gate process

1. A method comprising:

creating an opening inside a dielectric layer, said dielectric layer being formed on top of a substrate and said opening exposing a channel region of a transistor in said substrate;

depositing a work-function layer lining said opening and covering said channel region;

forming a gate conductor covering a first portion of said work-function layer, said first portion of said work-function layer being on top of said channel region; and

removing a second portion of said work-function layer, said second portion of said work-function layer surrounding said first portion of said work-function layer,

wherein said removal of said second portion of said work-function layer insulates said first portion of said work-function layer from rest of said work-function layer.

2. The method of claim 1 , wherein forming said gate conductor comprises:

forming sidewall spacers along sidewalls of said opening;

filling said opening, surrounded by said sidewall spacers, with a conductive material to form said gate conductor; and

applying a chemical-mechanical-polishing (CMP) process to remove excess of said conductive material that are on top of said dielectric layer.

3. The method of claim 2 , wherein removing said second portion of said work-function layer comprises:

applying said CMP process to polish down said conductive material to expose a top portion of said sidewall spacers;

removing said sidewall spacers exposed by said CMP process; and

etching said second portion of said work-function layer that is exposed by said removal of said sidewall spacers.

4. The method of claim 3 , wherein said sidewall spacers is made of silicon-nitride (SiN) and wherein said removing said sidewall spacers comprises applying a hot phosphorus solution to etch said sidewall spacers, said hot phosphorus solution causing no or substantially little etching effect to said gate conductor.

5. The method of claim 3 , wherein etching said second portion of said work-function layer comprises applying a directional etching process in said etching, wherein said directional etching process lowers a height of said work-function layer next to said sidewalls of said opening.

6. The method of claim 1 , wherein said work-function layer is a titanium-nitride (TiN) layer or a TiN layer doped with Al, and has a thickness ranging from about 1 nm to about 5 nm.

7. The method of claim 2 , wherein said dielectric layer is of a first dielectric material, further comprising covering said gate conductor with a second dielectric material, said second dielectric material filling a space created by said removal of said second portion of said work-function layer and said sidewall spacers, said second dielectric material insulating said first portion of said work-function layer from said rest of said work-function layer that is outside said second portion of said work-function layer.

8. The method of claim 7 , further comprising:

removing said first dielectric material of said dielectric layer;

removing said rest of said work-function layer; and

forming a new dielectric layer surrounding said second dielectric material in replacement of said first dielectric material and said rest of said work-function layer.

9. The method of claim 8 , further comprising forming one or more conductive contacts inside said new dielectric layer, said one or more conductive contacts contacting a source/drain of said transistor.

10. The method of claim 1 , further comprising forming one or more conductive contacts inside said dielectric layer, said one or more conductive contacts contacting a raised source/drain of said transistor.

11. A method comprising:

providing a transistor structure having a sacrificial gate, formed on top of a channel region in a substrate, and source and drain regions next to said sacrificial gate;

forming a dielectric layer surrounding said sacrificial gate;

removing said sacrificial gate to create an opening inside said dielectric layer, said opening exposing said channel region;

depositing a work-function layer lining said opening;

forming a gate conductor directly on top of a first portion of said work-function layer, said first portion of said work-function layer being on top of said channel region; and

removing a second portion of said work-function layer, said removal of said second portion of said work-function layer insulating said first portion of said work-function layer from rest of said work-function layer.

12. The method of claim 11 , wherein forming said gate conductor comprises:

forming spacers along sidewalls of said opening; and

filling said opening, surrounded by said spacers, with a conductive material to form said gate conductor.

13. The method of claim 12 , wherein removing said second portion of said work-function layer comprises:

removing said spacers after forming said gate conductor; and

etching said second portion of said work-function layer that is underneath said spacers.

14. The method of claim 13 , wherein said spacers comprise silicon-nitride (SiN) material and removing said spacers comprises applying a hot phosphorus solution to etch said spacers, said hot phosphorus solution causing little or no etching effect to said gate conductor.

15. The method of claim 13 , wherein etching said second portion of said work-function layer comprises applying a directional etching process in said etching, wherein said directional etching process lowers a height of said work-function layer that is next to said sidewalls of said opening and lowers a height of said gate conductor.

16. The method of claim 11 , wherein said work-function layer is a titanium-nitride (TiN) layer or a TiN layer doped with Al, and has a thickness ranging from about 1 nm to about 5 nm.

17. The method of claim 13 , wherein said dielectric layer is of a first dielectric material, further comprising covering said gate conductor with a second dielectric material, said second dielectric material filling a space created by said removal of said second portion of said work-function layer and said spacers, said second dielectric material covering said gate conductor and insulating said first portion of said work-function layer from said rest of said work-function layer that is outside said second portion of said work-function layer.

18. The method of claim 17 , further comprising removing said rest of said work-function layer.

19. The method of claim 18 , wherein removing said rest of said work-function layer comprises

selectively removing said first dielectric material of said dielectric layer to expose said rest of said work-function layer that is next to said opening;

selectively removing said exposed work-function layer; and

depositing a new dielectric layer to surround said second dielectric material that covers said gate conductor.

20. The method of claim 18 , further comprising forming one or more conductive contacts inside said new dielectric layer, said one or more conductive contacts contacting at least one source/drain region of said transistor.

21. The method of claim 11 , further comprising forming one or more conductive contacts inside said dielectric layer, said one or more conductive contacts contacting at least one raised source/drain region of said transistor.