IP Library Granted Patent US 8,797,285
Granted Patent B2
US 8,797,285 · App. 13/089,061 · Granted Aug 5, 2014

Panel

Inventors: David Brent Guard (Southampton, GB); Esat Yilmaz (Santa Cruz, CA); Tsung-Ching Wu (Saratoga, CA)
Assignee: Atmel Corporation
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Quick Facts
Patent No.
US 8,797,285
App. No.
13/089,061
Granted
Aug 5, 2014
Kind
B2
Abstract

An electrode pattern for a position sensing panel may have an array of mesh cells formed by sinusoidaly shaped conductive lines extending between vertices of the mesh cells.

Claims (37)

1. A panel of a touch sensitive screen, comprising:

a transparent insulating substrate having a first and a second face; and

a first conductive pattern arranged as a layer on the first face, the first conductive pattern comprising a plurality of first cells each formed from a plurality of first vertices in the layer on the first face, a conductive first line connecting each first vertex to at least one adjacent first vertex, the first vertices having a substantially randomized distribution such that each conductive first line has a substantially random orientation relative to pixels of a display located below the transparent insulating substrate;

a second conductive pattern arranged as a layer on the second face, the second conductive pattern comprising conductive second lines connected to second vertices to form a mesh of second cells in the layer on the second face, each of the conductive second lines being arranged to connect at least two of the second vertices such that each second vertex is connected to at least one other second vertex via a conductive second line.

2. The panel of claim 1 , wherein the at least one of the first and second conductive lines are comprised of copper.

3. The panel of claim 1 , wherein an angle formed by at least one of the first and second conductive lines that overlap each other at each vertex is substantially 90°.

4. The panel of claim 1 , wherein at least one of the first and second conductive lines varies in width along its length from one vertex to another vertex.

5. The panel of claim 1 , wherein a distance between at least one of the first vertices and an adjacent first vertex and a distance between the at least one of the first vertices and another adjacent first vertex are substantially randomized.

6. The panel of claim 5 , wherein the distance between the at least one of the first vertices and the adjacent vertex and the distance between the at least one of the first vertices and the other adjacent vertex are within a predetermined range.

7. The panel of claim 1 , wherein the second face is arranged on a surface of the transparent substrate opposite the first face.

8. The panel of claim 1 , wherein each first vertex is displaced in a substantially randomized direction, a distance between at least one of the first vertices and an adjacent first vertex and a distance between the at least one of the first vertices and another adjacent first vertex are substantially randomized.

9. The panel of claim 1 , wherein a variation of an area of each first cell is within 50% of a mean value of all first cells.

10. A panel of a touch sensitive screen, comprising:

a first transparent insulating substrate having a first face;

a first conductive pattern arranged as a layer on the first face, the first conductive pattern comprising a plurality of first cells each formed from a plurality of first vertices in the layer on the first face, a conductive first line connecting each first vertex to at least one adjacent first vertex, the first vertices having a substantially randomized distribution such that each conductive first line has a substantially random orientation relative to pixels of a display located below the transparent insulating substrate;

a second transparent insulating substrate having a second face; and

a second conductive pattern arranged as a layer on the second face, the second conductive pattern comprising conductive lines connected at vertices to form a mesh of cells in the layer on the second face, each of the conductive lines being arranged to connect two of the vertices such that each vertex is connected to at least one other vertex via a conductive line, wherein the second conductive pattern is in line with the first conductive pattern.

11. The panel of claim 10 , wherein each conductive line varies in width along the length of the respective conductive line from one vertex to another vertex.

12. The panel of claim 10 , wherein the width of the conductive line is narrower at a vertex than in the center of the conductive line.

13. The panel of claim 10 , wherein the width of conductive lines that overlap each other at each vertex is narrower at the vertex than along the length of the line not at the vertex.

14. The panel of claim 10 , wherein the width of the conductive lines is from about 1 μm to about 10 μm.

15. The panel of claim 10 , wherein the conductive lines are comprised of copper.

16. The panel of claim 10 , wherein a distance between at least one of the first vertices and an adjacent first vertex and a distance between the at least one of the first vertices and another adjacent first vertex are substantially randomized.

17. The panel of claim 16 , wherein the distance between the at least one of the first vertices and the adjacent vertex and the distance between the at least one of the first vertices and the other adjacent vertex are within a predetermined range.

18. The panel of claim 10 , wherein each first vertex is displaced in a substantially randomized direction, a distance between at least one of the first vertices and an adjacent first vertex and a distance between the at least one of the first vertices and another adjacent first vertex are substantially randomized.

19. The panel of claim 10 , wherein a variation of an area of each first cell is within 50% of a mean value of all first cells.

20. A method of electrode patterns for a touch panel of a touch sensitive screen, comprising:

forming a first conductive pattern arranged as a layer on a first face of a transparent insulating substrate, the first conductive pattern comprising a plurality of first cells each formed from a plurality of first vertices in the layer on the first face, a conductive first line connecting each first vertex to at least one-adjacent first vertex, the first vertices having a substantially randomized distribution such that each conductive first line has a substantially random orientation relative to pixels of a display located below the transparent insulating substrate; and

forming a second conductive pattern arranged as a layer on a second face of the transparent insulating substrate, the second conductive pattern comprising conductive second lines connected to second vertices to form a mesh of second cells in the layer on the second face, each of the conductive second lines being arranged to connect at least two of the second vertices such that each second vertex is connected to at least one other second vertex via a second conductive line.

21. The method of claim 20 , wherein the displaced locations are determined by an iterative process at random distances within a predefined range from the initial locations.

22. The method of claim 20 , wherein the conductive lines are comprised of copper.

23. The method of claim 20 , further comprising a second electrode pattern having a plurality of vertices, the second pattern arranged to overlap the first conductive pattern such that the vertices of the second pattern are located at a relative center of the cell of the first pattern.

24. The method of claim 20 , wherein forming the first conductive pattern comprises:

determining an initial location for each of the plurality of first vertices;

determining a substantially randomized displaced location for each of the plurality of first vertices from its initial location; and

forming a plurality of cells in the layer on the first face according to the first electrode pattern; and

connecting each first vertex to at least one adjacent first vertex with one of the conductive first lines.

Assignments (14)
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: ATMEL CORPORATION
Reel/Frame 059262/0105 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 5, 2019
From: MICROCHIP TECHNOLOGY INC.; ATMEL CORPORATION; MICROCHIP TECHNOLOGY GERMANY GMBH
To: NEODRÓN LIMITED
Reel/Frame 048259/0840 →
RELEASE OF SECURITY INTEREST IN CERTAIN PATENT RIGHTS Recorded Dec 21, 2018
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; ATMEL CORPORATION
Reel/Frame 047976/0884 →
RELEASE OF SECURITY INTEREST IN CERTAIN PATENT RIGHTS Recorded Dec 21, 2018
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; ATMEL CORPORATION
Reel/Frame 047976/0937 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: ATMEL CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041715/0747 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Apr 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: ATMEL CORPORATION
Reel/Frame 038376/0001 →
PATENT SECURITY AGREEMENT Recorded Jan 3, 2014
From: ATMEL CORPORATION
To: MORGAN STANLEY SENIOR FUNDING, INC. AS ADMINISTRATIVE AGENT
Reel/Frame 031912/0173 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 25, 2011
From: WU, TSUNG-CHING
To: ATMEL CORPORATION
Reel/Frame 026805/0467 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 25, 2011
From: GUARD, DAVID BRENT; YILMAZ, ESAT
To: QRG LIMITED
Reel/Frame 026805/0551 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 22, 2011
From: QRG LIMITED
To: ATMEL CORPORATION
Reel/Frame 026474/0832 →
Continuity (1)
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