Semiconductor device including stacked semiconductor chips
A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups.
1. A method comprising:
forming a plurality of semiconductor chips, each of the semiconductor chips comprising:
a first surface and a second surface opposite to the first surface;
a plurality of first terminals arranged apart from each other in substantially parallel to the first surface, the first terminals being provided on a side of the first surface;
a plurality of first conductive lines each extending vertically with respect to the first surface, each of the first conductive lines being vertically aligned with a corresponding one of the first terminals and electrically isolated from the corresponding one of the first terminals; and
a plurality of second conductive lines, each of the second conductive lines extending in substantially parallel to the first surface to electrically connect an associated one of the first conductive lines to a different one of the first terminals that is not vertically aligned with the associated one of the first conductive lines; and
stacking the semiconductor chips with each other such that the first conductive lines of a lower one of the semiconductor chips are electrically connected to the first terminals of an upper one of the semiconductor chips, respectively, and that each of the first terminals of the lowermost one of the semiconductor chips and an associated one of the first conductive lines of the uppermost one of the semiconductor chips, that are vertically aligned with each other, are electrically connected through the second conductive lines.
2. The method as claimed in claim 1 , wherein each of the semiconductor chips further comprises a plurality of second terminals provided on a side of the second surface, each of the second terminals being vertically aligned with an associated one of the first conductive lines and electrically connected to the associated one of the first conductive lines; and the stacking the semiconductor chips comprises connecting the second terminals the lower one of the semiconductor chips to the first terminals of the upper one of the semiconductor chips, respectively.
3. The method as claimed in claim 1 , wherein the first terminals of each of the semiconductor chips are arranged to correspond to vertices of a polygon.
4. The method as claimed in claim 2 , wherein the first terminals of each of the semiconductor chips are arranged to correspond to vertices of a polygon and the second terminals of each of the semiconductor chips are arranged to correspond to vertices of a polygon.
5. A method comprising:
forming a first semiconductor chip that comprises:
a first surface and a second surface opposite to the first surface;
a plurality of first terminals arranged apart from each other in substantially parallel to the first surface, the first terminals being provided on a side of the first surface;
a plurality of second terminals provided apart from each other in substantially parallel to the second surface, the second terminals being provided on a side of the second surface;
a plurality of first conductive lines each extending vertically with respect to the first surface, each of the first conductive lines being vertically aligned with a corresponding one of the first terminals and electrically isolated from the corresponding one of the first terminals, each of the first conductive lines being vertically aligned with a corresponding one of the second terminals and electrically connected to the corresponding one of the second terminals; and
a plurality of second conductive lines, each of the second conductive lines extending in substantially parallel to the first surface to electrically connect an associated one of the first conductive lines to a different one of the first terminals that is not vertically aligned with the associated one of the first conductive lines;
forming a second semiconductor chip that comprises:
a third surface and a fourth surface opposite to the third surface;
a plurality of third terminals provided apart from each other in substantially parallel to the third surface, the third terminals being provided on a side of the third surface;
a plurality of third conductive lines each extending vertically with respect to the third surface, each of the third conductive lines being vertically aligned with a corresponding one of the third terminals and electrically isolated from the corresponding one of the third terminals; and
a plurality of fourth conductive lines, each of the fourth conductive lines extending in substantially parallel to the third surface to electrically connect an associated one of the third conductive lines to a different one of the third terminals that is not vertically aligned with the associated one of the third conductive lines; and
stacking the first and second semiconductor chips with each other such that the second terminals of the first semiconductor chip are electrically connected to the third terminals of the second semiconductor chip, respectively, and that each of the first terminals of the first semiconductor chip and an associated one of the third conductive lines of the second semiconductor chip, that are vertically aligned with each other, are electrically connected through the second and fourth conductive lines.
6. The method as claimed in claim 5 , wherein the first terminals of the first semiconductor chip are arranged to correspond to vertices of a polygon, the second terminals of the first semiconductor chip are arranged to correspond to vertices of a polygon, and the third terminals of the second semiconductor chip are arranged to correspond to vertices of a polygon.
7. The method as claimed in claim 5 , wherein the second semiconductor chip further comprises a plurality of fourth terminals provided on a side of the fourth surface, each of the fourth terminals being vertically aligned with a corresponding one of the third conductive lines and electrically connected to the corresponding one of the third conductive lines.
8. The method as claimed in claim 7 , wherein the first terminals of the first semiconductor chip are arranged to correspond to vertices of a polygon, the second terminals of the first semiconductor chip are arranged to correspond to vertices of a polygon, the third terminals of the second semiconductor chip are arranged to correspond to vertices of a polygon, and the fourth terminals of the second semiconductor chip are arranged to correspond to vertices of a polygon.
9. The method as claimed in claim 5 ,
wherein the method further comprises forming the first semiconductor chip in plural to prepare a plurality of the first semiconductor chips; and
wherein the stacking comprises:
stacking the first semiconductor chips with each other such that the second terminals of a lower one of the first semiconductor chips are connected to the first terminals of an upper one of the first semiconductor chips, respectively; and
stacking the second semiconductor chip over the uppermost one of the first semiconductor chips such that the second terminals of the uppermost one of the first semiconductor chips are connected to the third terminals of the second semiconductor chip, respectively, and that each of the first terminals of the lowermost one of the first semiconductor chips and an associated one of the third conductive lines of the second semiconductor chip, that are vertically aligned with each other, are electrically connected through the second and fourth conductive lines.
10. The method as claimed in claim 9 , wherein the first terminals of each the first semiconductor chips are arranged to correspond to vertices of a polygon, the second terminals of each of the first semiconductor chips are arranged to correspond to vertices of a polygon, and the third terminals of the second semiconductor chip are arranged to correspond to vertices of a polygon.
11. The method as claimed in claim 9 , wherein the second semiconductor chip further comprises a plurality of fourth terminals provided on a side of the fourth surface, each of the fourth terminals being vertically aligned with a corresponding one of the third conductive lines and electrically connected to the corresponding one of the third conductive lines.
12. The method as claimed in claim 11 , wherein the first terminals of each of the first semiconductor chip are arranged to correspond to vertices of a polygon, the second terminals of each of the first semiconductor chip are arranged to correspond to vertices of a polygon, the third terminals of the second semiconductor chip are arranged to correspond to vertices of a polygon, and the fourth terminals of the second semiconductor chip are arranged to correspond to vertices of a polygon.