Multi-purpose architecture for CCD image sensors
View Patent ↗A charge-coupled device (CCD) image sensor includes multiple vertical charge-coupled device (VCCD) shift registers and independently-controllable gate electrodes disposed over the VCCD shift registers and arranged into physically separate and distinct sections that are non-continuous across the plurality of VCCD shift registers. The CCD image sensor can be configured to operate in two or more operating modes, including a full resolution charge multiplication mode.
1. An image sensor comprising:
a plurality of vertical charge-coupled device (VCCD) shift registers extending longitudinally along a direction of charge transfer; and
a plurality of independently-controllable gate electrodes disposed over the VCCD shift registers and arranged into physically separate and distinct sections, the physically separate and distinct sections being separated by a physical gap in the gate electrodes extending vertically between each of the electrodes of one section and each of the electrodes of the other section the sections to electrically isolate the gate electrodes of one section from the gate electrodes of the other section; and
wherein the physical gap extends longitudinally along the direction of charge transfer and across the pixel array.
2. The image sensor as in claim 1 , further comprising a plurality of horizontal charge-coupled device (HCCD) shift registers each including a plurality of charge storage elements, wherein each charge storage element is connected to a respective VCCD shift register to receive charge directly from the respective VCCD shift register.
3. The image sensor as in claim 1 , further comprising one or more timing generators configured to produce VCCD clocking signals applied to respective independently-controllable gate electrodes for shifting charge through the VCCD shift registers and into respective HCCD shift registers.
4. The image sensor as in claim 2 , further comprising one or more timing generators configured to produce VCCD clocking signals applied to respective independently-controllable gate electrodes for shifting charge through the VCCD shift registers and into respective HCCD shift registers and configured to produce HCCD clocking signals applied to respective gate electrodes for shifting charge through the HCCD shift registers, wherein the one or more timing generators is configured to produce VCCD and HCCD clocking signals for a full resolution image readout mode and for a full resolution charge multiplication mode.
5. The image sensor as in claim 2 , wherein two HCCD shift registers are disposed on one side of the VCCD shift registers and two HCCD shift registers are disposed on an opposite side of the VCCD shift registers.
6. The image sensor as in claim 4 , wherein two of the HCCD shift registers are disposed on one side of the VCCD shift registers and two of the HCCD shift registers are disposed on an opposite side of the VCCD shift registers and wherein all of the shift elements in at least two HCCD shift registers receive charge directly from respective VCCD shift registers during the full resolution image readout mode and all of the shift elements in two HCCD shift registers on opposite sides of the VCCD shift registers receive charge directly from respective VCCD shift registers during a full resolution charge multiplication mode.
7. An image sensor comprising:
a pixel array including a plurality of photosensitive areas with each of said photosensitive areas of the pixel array being spaced from each other in a uniform pattern across the pixel array;
the pixel array including a plurality of vertical charge-coupled device (VCCD) shift registers extending;
a first section of independently-controllable gate electrodes disposed over a portion of the VCCD shift registers and extending longitudinally along a direction transverse to the direction of charge transfer;
a second section of independently-controllable gate electrodes disposed over another discrete portion of the VCCD shift registers and extending longitudinally along a direction transverse to the direction of charge transfer; and
a physical gap across the pixel array between the first section of independently-controllable gate electrodes and the second section of independently-controllable gate electrodes such that the gate electrodes in the first and second sections are non-continuous across the entire pixel array.
8. The image sensor as in claim 7 , further comprising a plurality of horizontal charge-coupled device (HCCD) shift registers each including a plurality of charge storage elements, wherein each charge storage element is connected to a respective VCCD shift register to receive charge directly from the respective VCCD shift register.
9. The image sensor as in claim 7 , further comprising one or more timing generators configured to produce VCCD clocking signals applied to respective independently-controllable gate electrodes for shifting charge through the VCCD shift registers and into respective HCCD shift registers.
10. The image sensor as in claim 8 , further comprising one or more timing generators configured to produce VCCD clocking signals applied to respective independently-controllable gate electrodes for shifting charge through the VCCD shift registers and into respective HCCD shift registers and configured to produce HCCD clocking signals applied to respective gate electrodes for shifting charge through the HCCD shift registers.
11. An image capture device configured to operate in two or more modes, wherein one of the modes is a full resolution charge multiplication mode, the image capture device comprising:
a plurality of vertical charge-coupled device (VCCD) shift registers extending longitudinally along a direction of charge transfer;
a plurality of independently-controllable gate electrodes disposed over the VCCD shift registers and extending longitudinally along a direction transverse to the direction of charge transfer;
a physical gap in the gate electrodes physically separating and electrically isolating a first section of gate electrodes and a second section of gate electrodes, the physical gap extending along the direction of charge transfer between the gate electrodes of the first section and the gate electrodes of the second section;
a plurality of horizontal charge-coupled device (HCCD) shift registers each including a plurality of charge storage elements; and
one or more timing generators configured to produce VCCD clocking signals applied to respective independently-controllable gate electrodes for shifting charge through the VCCD shift registers and configured to produce HCCD clocking signals applied to respective gate electrodes for shifting charge through the HCCD shift registers.
12. The image capture device as in claim 11 , further comprising a processor operable to control the production of VCCD and HCCD clocking signals by the one or more timing generators based on the respective operating mode of the image capture device.
13. The image capture device as in claim 11 , wherein each charge storage element in the plurality of horizontal charge-coupled device (HCCD) shift registers is connected to a respective VCCD shift register to receive charge directly from the respective VCCD shift register.
14. The image sensor as in claim 1 , wherein the gate electrodes include a first layer in the first and second sections and a second layer in the first and second sections with the physical gap formed in the first layer and another physical gap formed in the second layer.
15. The image sensor as in claim 14 , wherein the gate electrodes include a third layer in the first and second sections with another physical gap formed in the third layer.
16. The image sensor as in claim 7 , wherein the gate electrodes include a first layer in the first and second sections and a second layer in the first and second sections with the physical gap formed in the first layer and another physical gap formed in the second layer.
17. The image sensor as in claim 16 , wherein the gate electrodes include a third layer in the first and second sections with another physical gap formed in the third layer.
18. The image sensor as in claim 11 , wherein the gate electrodes include a first layer in the first and second sections and a second layer in the first and second sections with the physical gap formed in the first layer and another physical gap formed in the second layer.
19. The image sensor as in claim 18 , wherein the gate electrodes include a third layer in the first and second sections with another physical gap formed in the third layer.
20. The image sensor as in claim 7 , wherein the VCCD shift register extends longitudinally along a direction of charge transfer and wherein the physical gap extends longitudinally along the direction of charge transfer.
21. The image sensor as in claim 1 , further comprising a pixel array including a plurality of photosensitive areas with each of said photosensitive areas of the pixel array being spaced from each other in a uniform pattern across the pixel array and wherein the physical gap extends across the pixel array.
22. The image sensor as in claim 11 , further comprising a pixel array including a plurality of photosensitive areas with each of said photosensitive areas of the pixel array being spaced from each other in a uniform pattern across the pixel array.