IP Library Granted Patent US 8,674,232
Granted Patent B2
US 8,674,232 · App. 13/116,224 · Granted Mar 18, 2014

Device-embedded flexible printed circuit board and manufacturing method thereof

Inventors: Yang-sik Cho (Changwon, KR); Sung-taik Hong (Changwon, KR); Gun-ho Wang (Changwon, KR)
Assignee: Samsung Techwin Co., Ltd.
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Quick Facts
Patent No.
US 8,674,232
App. No.
13/116,224
Granted
Mar 18, 2014
Kind
B2
Abstract

A device-embedded flexible printed circuit board (FPCB) and a method of manufacturing the device-embedded FPCB are provided. The device-embedded FPCB includes: a first conductive layer; a first insulating layer which is disposed on the first conductive layer and includes at least one bump hole and at least one groove; a first plating layer which is formed in the at least one groove of the first insulating layer; and a device which includes at least one bump which is inserted into the at least one bump hole to be connected to the first conductive layer.

Claims (24)

1. A method of manufacturing a device-embedded flexible printed circuit board, the method comprising:

forming at least one bump hole in a first insulating layer disposed on a first conductive layer and forming at least one groove;

disposing a plating resist on the at least one bump hole to cover the at least one bump hole and performing plating to form a plating layer in the at least one groove;

removing the plating resist; and

disposing a device comprising at least one bump which is inserted into the at least one bump hole.

2. The method of claim 1 , wherein the first conductive layer comprises a copper layer of a flexible copper clad laminate (FCCL), and the first insulating layer comprises a core layer of the FCCL.

3. The method of claim 1 , further comprising:

disposing a second insulating layer on the first insulating layer to cover the device and disposing a second conductive layer on the second insulating layer;

forming at least one via-hole which penetrates the second conductive layer and the second insulating layer and reaches the first plating layer; and

forming a second plating layer in the at least one via-hole to electrically connect the second conductive layer to the first plating layer.

4. The method of claim 3 , wherein the at least one groove is formed corresponding to a first circuit pattern, and thus, the first plating layer is formed as the first circuit pattern, and

wherein the method further comprising:

forming a second circuit pattern in the first conductive layer; and

forming a third circuit pattern in the second conductive layer.

5. The method of claim 3 , wherein the second insulating layer comprises a resin layer of a resin-coated copper foil (RCC), and the second conductive layer comprises a copper layer of the RCC.

6. The method of claim 3 , wherein the second conductive layer comprises a copper layer of a flexible copper clad laminate (FCCL) which comprises a core layer adhering onto the second insulating layer.

7. The method of claim 3 , wherein the second insulating layer is a bonding sheet.

8. The method of claim 3 , further comprising respectively disposing protective layers underneath the first conductive layer and on the second conductive layer.

9. The method of claim 1 , between removing the plating resist and disposing the device on the first insulating layer, further comprising disposing at least one conductive ball in the at least one bump hole to electrically connect the at least one bump of the device to the first conductive layer.

10. The method of claim 1 , between removing the plating resist and disposing the device on the first insulating layer, further comprising coating an adhesive material on a portion of the first insulating layer in which the at least one bump hole has been formed.

11. The method of claim 1 , further comprising connecting the first conductive layer to the first plating layer through the at least one groove.

12. The method of claim 1 , wherein the at least one groove is formed corresponding to a first circuit pattern, and thus, the first plating layer is formed as the first circuit pattern.

13. The method of claim 12 , further comprising forming a second circuit pattern in the first conductive layer.

14. The method of claim 13 , further comprising forming a third circuit pattern in the second conductive layer.

Assignments (3)
CHANGE OF NAME Recorded Apr 21, 2015
From: MDS CO. LTD.
To: HAESUNG DS CO., LTD.
Reel/Frame 035475/0415 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2014
From: SAMSUNG TECHWIN CO., LTD.
To: MDS CO. LTD.
Reel/Frame 033327/0442 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 26, 2011
From: CHO, YANG-SIK; HONG, SUNG-TAIK; WANG, GUN-HO
To: SAMSUNG TECHWIN CO., LTD.
Reel/Frame 026344/0017 →
Priority Claims (1)
KR 10-2010-0079286 · Aug 17, 2010 · national
Continuity (1)
Related Publication 20120043114A1 · Feb 23, 2012